
# Generated from JALLIB device files
PIC_UNKOWN = 0
PIC_12 = 1
PIC_14 = 2
PIC_16 = 3

class pic_10f200 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 256
   data = [ [0x10 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
   } 
   shadow_regs = { 
   } 

class pic_10f202 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 512
   data = [ [0x08 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
   } 
   shadow_regs = { 
   } 

class pic_10f204 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 256
   data = [ [0x10 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
      'CMCON0':0x7,
   } 
   shadow_regs = { 
   } 

class pic_10f206 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 512
   data = [ [0x08 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
      'CMCON0':0x7,
   } 
   shadow_regs = { 
   } 

class pic_10f220 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 256
   data = [ [0x10 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
      'ADCON0':0x7,
      'ADRES':0x8,
   } 
   shadow_regs = { 
   } 

class pic_10f222 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 512
   data = [ [0x09 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
      'ADCON0':0x7,
      'ADRES':0x8,
   } 
   shadow_regs = { 
   } 

class pic_12f508 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 512
   data = [ [0x07 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
   } 
   shadow_regs = { 
   } 

class pic_12f509 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 1024
   data = [ [0x10 , 0x1F], [0x30 , 0x3F],  ]
   shared = [ 0x07 , 0x0F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x20,],
      0x20:[0x0,0x20,],
      
      0x1:[0x1,0x21,],
      0x21:[0x1,0x21,],
      
      0x2:[0x2,0x22,],
      0x22:[0x2,0x22,],
      
      0x3:[0x3,0x23,],
      0x23:[0x3,0x23,],
      
      0x4:[0x4,0x24,],
      0x24:[0x4,0x24,],
      
      0x5:[0x5,0x25,],
      0x25:[0x5,0x25,],
      
      0x6:[0x6,0x26,],
      0x26:[0x6,0x26,],
   } 

class pic_12f510 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 1024
   data = [ [0x10 , 0x1F], [0x30 , 0x3F],  ]
   shared = [ 0x0A , 0x0F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
      'CM1CON0':0x7,
      'ADCON0':0x8,
      'ADRES':0x9,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x20,],
      0x20:[0x0,0x20,],
      
      0x1:[0x1,0x21,],
      0x21:[0x1,0x21,],
      
      0x2:[0x2,0x22,],
      0x22:[0x2,0x22,],
      
      0x3:[0x3,0x23,],
      0x23:[0x3,0x23,],
      
      0x4:[0x4,0x24,],
      0x24:[0x4,0x24,],
      
      0x5:[0x5,0x25,],
      0x25:[0x5,0x25,],
      
      0x6:[0x6,0x26,],
      0x26:[0x6,0x26,],
      
      0x7:[0x7,0x27,],
      0x27:[0x7,0x27,],
      
      0x8:[0x8,0x28,],
      0x28:[0x8,0x28,],
      
      0x9:[0x9,0x29,],
      0x29:[0x9,0x29,],
   } 

class pic_12f519 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 1024
   eeprom_location = 0x400
   eeprom_size = 64
   data = [ [0x10 , 0x1F], [0x30 , 0x3F],  ]
   shared = [ 0x07 , 0x0F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'GPIO':0x6,
      'EECON':0x21,
      'EEDATA':0x25,
      'EEADR':0x26,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x20,],
      0x20:[0x0,0x20,],
      
      0x2:[0x2,0x22,],
      0x22:[0x2,0x22,],
      
      0x3:[0x3,0x23,],
      0x23:[0x3,0x23,],
      
      0x4:[0x4,0x24,],
      0x24:[0x4,0x24,],
   } 

class pic_12f609 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   data = [ [0x40 , 0x6F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'GPIO':0x5,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'VRCON':0x19,
      'CM1CON0':0x1A,
      'CM1CON1':0x1C,
      'TRISIO':0x85,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCTUNE':0x90,
      'WPU':0x95,
      'IOC':0x96,
      'ANSEL':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_12f615 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   data = [ [0x40 , 0x6F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'GPIO':0x5,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x13,
      'CCPR1H':0x14,
      'CCP1CON':0x15,
      'PWM1CON':0x16,
      'ECCPAS':0x17,
      'VRCON':0x19,
      'CMCON0':0x1A,
      'CMCON1':0x1C,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISIO':0x85,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'APFCON':0x93,
      'WPU':0x95,
      'IOC':0x96,
      'ADRESL':0x9E,
      'ANSEL':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_12f629 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x5D],  ]
   shared = [ 0x5E , 0x5F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'GPIO':0x5,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'CMCON':0x19,
      'TRISIO':0x85,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCAL':0x90,
      'WPU':0x95,
      'IOC':0x96,
      'VRCON':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_12f635 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x40 , 0x6F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'GPIO':0x5,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'WDTCON':0x18,
      'CMCON0':0x19,
      'CMCON1':0x1A,
      'TRISIO':0x85,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'LVDCON':0x94,
      'WPUDA':0x95,
      'IOCA':0x96,
      'WDA':0x97,
      'VRCON':0x99,
      'EEDAT':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'CRCON':0x110,
      'CRDAT0':0x111,
      'CRDAT1':0x112,
      'CRDAT2':0x113,
      'CRDAT3':0x114,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0xA:[0xA,0x10A,],
      0x10A:[0xA,0x10A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
   } 

class pic_12f675 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x5D],  ]
   shared = [ 0x5E , 0x5F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'GPIO':0x5,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'CMCON':0x19,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISIO':0x85,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCAL':0x90,
      'WPU':0x95,
      'IOC':0x96,
      'VRCON':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'ADRESL':0x9E,
      'ANSEL':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_12f683 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'GPIO':0x5,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x13,
      'CCPR1H':0x14,
      'CCP1CON':0x15,
      'WDTCON':0x18,
      'CMCON0':0x19,
      'CMCON1':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISIO':0x85,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'WPU':0x95,
      'IOC':0x96,
      'VRCON':0x99,
      'EEDAT':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'ADRESL':0x9E,
      'ANSEL':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_12hv609 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   data = [ [0x40 , 0x6F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'GPIO':0x5,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'VRCON':0x19,
      'CM1CON0':0x1A,
      'CM1CON1':0x1C,
      'TRISIO':0x85,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCTUNE':0x90,
      'WPU':0x95,
      'IOC':0x96,
      'ANSEL':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_12hv615 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   data = [ [0x40 , 0x6F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'GPIO':0x5,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x13,
      'CCPR1H':0x14,
      'CCP1CON':0x15,
      'PWM1CON':0x16,
      'ECCPAS':0x17,
      'VRCON':0x19,
      'CMCON0':0x1A,
      'CMCON1':0x1C,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISIO':0x85,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'APFCON':0x93,
      'WPU':0x95,
      'IOC':0x96,
      'ADRESL':0x9E,
      'ANSEL':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f505 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 1024
   data = [ [0x10 , 0x1F], [0x30 , 0x3F], [0x50 , 0x5F], [0x70 , 0x7F],  ]
   shared = [ 0x08 , 0x0F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x20,0x40,0x60,],
      0x20:[0x0,0x20,0x40,0x60,],
      0x40:[0x0,0x20,0x40,0x60,],
      0x60:[0x0,0x20,0x40,0x60,],
      
      0x1:[0x1,0x21,0x41,0x61,],
      0x21:[0x1,0x21,0x41,0x61,],
      0x41:[0x1,0x21,0x41,0x61,],
      0x61:[0x1,0x21,0x41,0x61,],
      
      0x2:[0x2,0x22,0x42,0x62,],
      0x22:[0x2,0x22,0x42,0x62,],
      0x42:[0x2,0x22,0x42,0x62,],
      0x62:[0x2,0x22,0x42,0x62,],
      
      0x3:[0x3,0x23,0x43,0x63,],
      0x23:[0x3,0x23,0x43,0x63,],
      0x43:[0x3,0x23,0x43,0x63,],
      0x63:[0x3,0x23,0x43,0x63,],
      
      0x4:[0x4,0x24,0x44,0x64,],
      0x24:[0x4,0x24,0x44,0x64,],
      0x44:[0x4,0x24,0x44,0x64,],
      0x64:[0x4,0x24,0x44,0x64,],
      
      0x5:[0x5,0x25,0x45,0x65,],
      0x25:[0x5,0x25,0x45,0x65,],
      0x45:[0x5,0x25,0x45,0x65,],
      0x65:[0x5,0x25,0x45,0x65,],
      
      0x6:[0x6,0x26,0x46,0x66,],
      0x26:[0x6,0x26,0x46,0x66,],
      0x46:[0x6,0x26,0x46,0x66,],
      0x66:[0x6,0x26,0x46,0x66,],
      
      0x7:[0x7,0x27,0x47,0x67,],
      0x27:[0x7,0x27,0x47,0x67,],
      0x47:[0x7,0x27,0x47,0x67,],
      0x67:[0x7,0x27,0x47,0x67,],
   } 

class pic_16f506 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 1024
   data = [ [0x10 , 0x1F], [0x30 , 0x3F], [0x50 , 0x5F], [0x70 , 0x7F],  ]
   shared = [ 0x0D , 0x0F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'CM1CON0':0x8,
      'ADCON0':0x9,
      'ADRES':0xA,
      'CM2CON0':0xB,
      'VRCON':0xC,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x20,0x40,0x60,],
      0x20:[0x0,0x20,0x40,0x60,],
      0x40:[0x0,0x20,0x40,0x60,],
      0x60:[0x0,0x20,0x40,0x60,],
      
      0x1:[0x1,0x21,0x41,0x61,],
      0x21:[0x1,0x21,0x41,0x61,],
      0x41:[0x1,0x21,0x41,0x61,],
      0x61:[0x1,0x21,0x41,0x61,],
      
      0x2:[0x2,0x22,0x42,0x62,],
      0x22:[0x2,0x22,0x42,0x62,],
      0x42:[0x2,0x22,0x42,0x62,],
      0x62:[0x2,0x22,0x42,0x62,],
      
      0x3:[0x3,0x23,0x43,0x63,],
      0x23:[0x3,0x23,0x43,0x63,],
      0x43:[0x3,0x23,0x43,0x63,],
      0x63:[0x3,0x23,0x43,0x63,],
      
      0x4:[0x4,0x24,0x44,0x64,],
      0x24:[0x4,0x24,0x44,0x64,],
      0x44:[0x4,0x24,0x44,0x64,],
      0x64:[0x4,0x24,0x44,0x64,],
      
      0x5:[0x5,0x25,0x45,0x65,],
      0x25:[0x5,0x25,0x45,0x65,],
      0x45:[0x5,0x25,0x45,0x65,],
      0x65:[0x5,0x25,0x45,0x65,],
      
      0x6:[0x6,0x26,0x46,0x66,],
      0x26:[0x6,0x26,0x46,0x66,],
      0x46:[0x6,0x26,0x46,0x66,],
      0x66:[0x6,0x26,0x46,0x66,],
      
      0x7:[0x7,0x27,0x47,0x67,],
      0x27:[0x7,0x27,0x47,0x67,],
      0x47:[0x7,0x27,0x47,0x67,],
      0x67:[0x7,0x27,0x47,0x67,],
      
      0x8:[0x8,0x28,0x48,0x68,],
      0x28:[0x8,0x28,0x48,0x68,],
      0x48:[0x8,0x28,0x48,0x68,],
      0x68:[0x8,0x28,0x48,0x68,],
      
      0x9:[0x9,0x29,0x49,0x69,],
      0x29:[0x9,0x29,0x49,0x69,],
      0x49:[0x9,0x29,0x49,0x69,],
      0x69:[0x9,0x29,0x49,0x69,],
      
      0xA:[0xA,0x2A,0x4A,0x6A,],
      0x2A:[0xA,0x2A,0x4A,0x6A,],
      0x4A:[0xA,0x2A,0x4A,0x6A,],
      0x6A:[0xA,0x2A,0x4A,0x6A,],
      
      0xB:[0xB,0x2B,0x4B,0x6B,],
      0x2B:[0xB,0x2B,0x4B,0x6B,],
      0x4B:[0xB,0x2B,0x4B,0x6B,],
      0x6B:[0xB,0x2B,0x4B,0x6B,],
      
      0xC:[0xC,0x2C,0x4C,0x6C,],
      0x2C:[0xC,0x2C,0x4C,0x6C,],
      0x4C:[0xC,0x2C,0x4C,0x6C,],
      0x6C:[0xC,0x2C,0x4C,0x6C,],
   } 

class pic_16f526 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 1024
   eeprom_location = 0x400
   eeprom_size = 64
   data = [ [0x10 , 0x1F], [0x30 , 0x3F], [0x50 , 0x5F], [0x70 , 0x7F],  ]
   shared = [ 0x0D , 0x0F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'OSCCAL':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'CM1CON0':0x8,
      'ADCON0':0x9,
      'ADRES':0xA,
      'CM2CON0':0xB,
      'VRCON':0xC,
      'EECON':0x21,
      'EEDATA':0x25,
      'EEADR':0x26,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x20,0x40,0x60,],
      0x20:[0x0,0x20,0x40,0x60,],
      0x40:[0x0,0x20,0x40,0x60,],
      0x60:[0x0,0x20,0x40,0x60,],
      
      0x1:[0x1,0x41,],
      0x41:[0x1,0x41,],
      
      0x2:[0x2,0x22,0x42,0x62,],
      0x22:[0x2,0x22,0x42,0x62,],
      0x42:[0x2,0x22,0x42,0x62,],
      0x62:[0x2,0x22,0x42,0x62,],
      
      0x3:[0x3,0x23,0x43,0x63,],
      0x23:[0x3,0x23,0x43,0x63,],
      0x43:[0x3,0x23,0x43,0x63,],
      0x63:[0x3,0x23,0x43,0x63,],
      
      0x4:[0x4,0x24,0x44,0x64,],
      0x24:[0x4,0x24,0x44,0x64,],
      0x44:[0x4,0x24,0x44,0x64,],
      0x64:[0x4,0x24,0x44,0x64,],
      
      0x5:[0x5,0x45,],
      0x45:[0x5,0x45,],
      
      0x6:[0x6,0x46,],
      0x46:[0x6,0x46,],
      
      0x7:[0x7,0x27,0x47,0x67,],
      0x27:[0x7,0x27,0x47,0x67,],
      0x47:[0x7,0x27,0x47,0x67,],
      0x67:[0x7,0x27,0x47,0x67,],
      
      0x8:[0x8,0x28,0x48,0x68,],
      0x28:[0x8,0x28,0x48,0x68,],
      0x48:[0x8,0x28,0x48,0x68,],
      0x68:[0x8,0x28,0x48,0x68,],
      
      0x9:[0x9,0x29,0x49,0x69,],
      0x29:[0x9,0x29,0x49,0x69,],
      0x49:[0x9,0x29,0x49,0x69,],
      0x69:[0x9,0x29,0x49,0x69,],
      
      0xA:[0xA,0x2A,0x4A,0x6A,],
      0x2A:[0xA,0x2A,0x4A,0x6A,],
      0x4A:[0xA,0x2A,0x4A,0x6A,],
      0x6A:[0xA,0x2A,0x4A,0x6A,],
      
      0xB:[0xB,0x2B,0x4B,0x6B,],
      0x2B:[0xB,0x2B,0x4B,0x6B,],
      0x4B:[0xB,0x2B,0x4B,0x6B,],
      0x6B:[0xB,0x2B,0x4B,0x6B,],
      
      0xC:[0xC,0x2C,0x4C,0x6C,],
      0x2C:[0xC,0x2C,0x4C,0x6C,],
      0x4C:[0xC,0x2C,0x4C,0x6C,],
      0x6C:[0xC,0x2C,0x4C,0x6C,],
      
      0x21:[0x21,0x61,],
      0x61:[0x21,0x61,],
      
      0x25:[0x25,0x65,],
      0x65:[0x25,0x65,],
      
      0x26:[0x26,0x66,],
      0x66:[0x26,0x66,],
   } 

class pic_16f54 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 512
   data = [ [0x7 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
   } 
   shadow_regs = { 
   } 

class pic_16f57 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 2048
   data = [ [0x10 , 0x1F], [0x30 , 0x3F], [0x50 , 0x5F], [0x70 , 0x7F],  ]
   shared = [ 0x8 , 0xF]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x20,0x40,0x60,],
      0x20:[0x0,0x20,0x40,0x60,],
      0x40:[0x0,0x20,0x40,0x60,],
      0x60:[0x0,0x20,0x40,0x60,],
      
      0x1:[0x1,0x21,0x41,0x61,],
      0x21:[0x1,0x21,0x41,0x61,],
      0x41:[0x1,0x21,0x41,0x61,],
      0x61:[0x1,0x21,0x41,0x61,],
      
      0x2:[0x2,0x22,0x42,0x62,],
      0x22:[0x2,0x22,0x42,0x62,],
      0x42:[0x2,0x22,0x42,0x62,],
      0x62:[0x2,0x22,0x42,0x62,],
      
      0x3:[0x3,0x23,0x43,0x63,],
      0x23:[0x3,0x23,0x43,0x63,],
      0x43:[0x3,0x23,0x43,0x63,],
      0x63:[0x3,0x23,0x43,0x63,],
      
      0x4:[0x4,0x24,0x44,0x64,],
      0x24:[0x4,0x24,0x44,0x64,],
      0x44:[0x4,0x24,0x44,0x64,],
      0x64:[0x4,0x24,0x44,0x64,],
      
      0x5:[0x5,0x25,0x45,0x65,],
      0x25:[0x5,0x25,0x45,0x65,],
      0x45:[0x5,0x25,0x45,0x65,],
      0x65:[0x5,0x25,0x45,0x65,],
      
      0x6:[0x6,0x26,0x46,0x66,],
      0x26:[0x6,0x26,0x46,0x66,],
      0x46:[0x6,0x26,0x46,0x66,],
      0x66:[0x6,0x26,0x46,0x66,],
      
      0x7:[0x7,0x27,0x47,0x67,],
      0x27:[0x7,0x27,0x47,0x67,],
      0x47:[0x7,0x27,0x47,0x67,],
      0x67:[0x7,0x27,0x47,0x67,],
   } 

class pic_16f59 : 

   cpu_type = PIC_12
   stack_size = 2
   code_size = 2048
   data = [ [0x10 , 0x1F], [0x30 , 0x3F], [0x50 , 0x5F], [0x70 , 0x7F],  ]
   shared = [ 0xA , 0xF]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x20,0x40,0x60,],
      0x20:[0x0,0x20,0x40,0x60,],
      0x40:[0x0,0x20,0x40,0x60,],
      0x60:[0x0,0x20,0x40,0x60,],
      
      0x1:[0x1,0x21,0x41,0x61,],
      0x21:[0x1,0x21,0x41,0x61,],
      0x41:[0x1,0x21,0x41,0x61,],
      0x61:[0x1,0x21,0x41,0x61,],
      
      0x2:[0x2,0x22,0x42,0x62,],
      0x22:[0x2,0x22,0x42,0x62,],
      0x42:[0x2,0x22,0x42,0x62,],
      0x62:[0x2,0x22,0x42,0x62,],
      
      0x3:[0x3,0x23,0x43,0x63,],
      0x23:[0x3,0x23,0x43,0x63,],
      0x43:[0x3,0x23,0x43,0x63,],
      0x63:[0x3,0x23,0x43,0x63,],
      
      0x4:[0x4,0x24,0x44,0x64,],
      0x24:[0x4,0x24,0x44,0x64,],
      0x44:[0x4,0x24,0x44,0x64,],
      0x64:[0x4,0x24,0x44,0x64,],
      
      0x5:[0x5,0x25,0x45,0x65,],
      0x25:[0x5,0x25,0x45,0x65,],
      0x45:[0x5,0x25,0x45,0x65,],
      0x65:[0x5,0x25,0x45,0x65,],
      
      0x6:[0x6,0x26,0x46,0x66,],
      0x26:[0x6,0x26,0x46,0x66,],
      0x46:[0x6,0x26,0x46,0x66,],
      0x66:[0x6,0x26,0x46,0x66,],
      
      0x7:[0x7,0x27,0x47,0x67,],
      0x27:[0x7,0x27,0x47,0x67,],
      0x47:[0x7,0x27,0x47,0x67,],
      0x67:[0x7,0x27,0x47,0x67,],
      
      0x8:[0x8,0x28,0x48,0x68,],
      0x28:[0x8,0x28,0x48,0x68,],
      0x48:[0x8,0x28,0x48,0x68,],
      0x68:[0x8,0x28,0x48,0x68,],
      
      0x9:[0x9,0x29,0x49,0x69,],
      0x29:[0x9,0x29,0x49,0x69,],
      0x49:[0x9,0x29,0x49,0x69,],
      0x69:[0x9,0x29,0x49,0x69,],
   } 

class pic_16f610 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   data = [ [0x40 , 0x6F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'VRCON':0x19,
      'CM1CON0':0x1A,
      'CM2CON0':0x1B,
      'CM2CON1':0x1C,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'WPUA':0x95,
      'IOCA':0x96,
      'SRCON0':0x99,
      'SRCON1':0x9A,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f616 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x13,
      'CCPR1H':0x14,
      'CCP1CON':0x15,
      'PWM1CON':0x16,
      'ECCPAS':0x17,
      'VRCON':0x19,
      'CM1CON0':0x1A,
      'CM2CON0':0x1B,
      'CM2CON1':0x1C,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'PR2':0x92,
      'WPUA':0x95,
      'IOCA':0x96,
      'SRCON0':0x99,
      'SRCON1':0x9A,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f627 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x14F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CMCON':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PCON':0x8E,
      'PR2':0x92,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'VRCON':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f627a : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x14F],  ]
   shared = [ 0x70 , 0x7E,0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CMCON':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PCON':0x8E,
      'PR2':0x92,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'VRCON':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f628 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x14F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CMCON':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PCON':0x8E,
      'PR2':0x92,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'VRCON':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f628a : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x14F],  ]
   shared = [ 0x70 , 0x7E,0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CMCON':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PCON':0x8E,
      'PR2':0x92,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'VRCON':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f630 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x5D],  ]
   shared = [ 0x5E , 0x5F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'CMCON':0x19,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCAL':0x90,
      'WPUA':0x95,
      'IOCA':0x96,
      'VRCON':0x99,
      'EEDAT':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f631 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x40 , 0x6F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'WPUA':0x95,
      'IOCA':0x96,
      'WDTCON':0x97,
      'EEDAT':0x10C,
      'EEADR':0x10D,
      'WPUB':0x115,
      'IOCB':0x116,
      'VRCON':0x118,
      'CM1CON0':0x119,
      'CM2CON0':0x11A,
      'CM2CON1':0x11B,
      'EECON1':0x18C,
      'EECON2':0x18D,
      'SRCON':0x19E,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f636 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'WDTCON':0x18,
      'CMCON0':0x19,
      'CMCON1':0x1A,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'LVDCON':0x94,
      'WPUDA':0x95,
      'IOCA':0x96,
      'WDA':0x97,
      'VRCON':0x99,
      'EEDAT':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'CRCON':0x110,
      'CRDAT0':0x111,
      'CRDAT1':0x112,
      'CRDAT2':0x113,
      'CRDAT3':0x114,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f639 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'WDTCON':0x18,
      'CMCON0':0x19,
      'CMCON1':0x1A,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'LVDCON':0x94,
      'WPUDA':0x95,
      'IOCA':0x96,
      'WDA':0x97,
      'VRCON':0x99,
      'EEDAT':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'CRCON':0x110,
      'CRDAT0':0x111,
      'CRDAT1':0x112,
      'CRDAT2':0x113,
      'CRDAT3':0x114,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0xC:[0xC,0x10C,],
      0x10C:[0xC,0x10C,],
      
      0xE:[0xE,0x10E,],
      0x10E:[0xE,0x10E,],
      
      0xE:[0xE,0x10E,],
      0x10E:[0xE,0x10E,],
      
      0xF:[0xF,0x10F,],
      0x10F:[0xF,0x10F,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
      
      0x8C:[0x8C,0x18C,],
      0x18C:[0x8C,0x18C,],
      
      0x8E:[0x8E,0x18E,],
      0x18E:[0x8E,0x18E,],
      
      0x8F:[0x8F,0x18F,],
      0x18F:[0x8F,0x18F,],
      
      0x90:[0x90,0x190,],
      0x190:[0x90,0x190,],
      
      0x94:[0x94,0x194,],
      0x194:[0x94,0x194,],
      
      0x95:[0x95,0x195,],
      0x195:[0x95,0x195,],
      
      0x96:[0x96,0x196,],
      0x196:[0x96,0x196,],
      
      0x97:[0x97,0x197,],
      0x197:[0x97,0x197,],
      
      0x99:[0x99,0x199,],
      0x199:[0x99,0x199,],
      
      0x9A:[0x9A,0x19A,],
      0x19A:[0x9A,0x19A,],
      
      0x9B:[0x9B,0x19B,],
      0x19B:[0x9B,0x19B,],
      
      0x9C:[0x9C,0x19C,],
      0x19C:[0x9C,0x19C,],
      
      0x9D:[0x9D,0x19D,],
      0x19D:[0x9D,0x19D,],
   } 

class pic_16f648a : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CMCON':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PCON':0x8E,
      'PR2':0x92,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'VRCON':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f676 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x5D],  ]
   shared = [ 0x5E , 0x5F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'CMCON':0x19,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCAL':0x90,
      'ANSEL':0x91,
      'WPUA':0x95,
      'IOCA':0x96,
      'VRCON':0x99,
      'EEDAT':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f677 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUA':0x95,
      'IOCA':0x96,
      'WDTCON':0x97,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDAT':0x10C,
      'EEADR':0x10D,
      'WPUB':0x115,
      'IOCB':0x116,
      'VRCON':0x118,
      'CM1CON0':0x119,
      'CM2CON0':0x11A,
      'CM2CON1':0x11B,
      'ANSEL':0x11E,
      'ANSELH':0x11F,
      'EECON1':0x18C,
      'EECON2':0x18D,
      'SRCON':0x19E,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f684 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x13,
      'CCPR1H':0x14,
      'CCP1CON':0x15,
      'PWM1CON':0x16,
      'ECCPAS':0x17,
      'WDTCON':0x18,
      'CMCON0':0x19,
      'CMCON1':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'PR2':0x92,
      'WPUA':0x95,
      'IOCA':0x96,
      'VRCON':0x99,
      'EEDAT':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f685 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'PWM1CON':0x1C,
      'ECCPAS':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'WPUA':0x95,
      'IOCA':0x96,
      'WDTCON':0x97,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'WPUB':0x115,
      'IOCB':0x116,
      'VRCON':0x118,
      'CM1CON0':0x119,
      'CM2CON0':0x11A,
      'CM2CON1':0x11B,
      'ANSEL':0x11E,
      'ANSELH':0x11F,
      'EECON1':0x18C,
      'EECON2':0x18D,
      'PSTRCON':0x19D,
      'SRCON':0x19E,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f687 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUA':0x95,
      'IOCA':0x96,
      'WDTCON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'SPBRGH':0x9A,
      'BAUDCTL':0x9B,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'WPUB':0x115,
      'IOCB':0x116,
      'VRCON':0x118,
      'CM1CON0':0x119,
      'CM2CON0':0x11A,
      'CM2CON1':0x11B,
      'ANSEL':0x11E,
      'ANSELH':0x11F,
      'EECON1':0x18C,
      'EECON2':0x18D,
      'SRCON':0x19E,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f688 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'BAUDCTL':0x11,
      'SPBRGH':0x12,
      'SPBRG':0x13,
      'RCREG':0x14,
      'TXREG':0x15,
      'TXSTA':0x16,
      'RCSTA':0x17,
      'WDTCON':0x18,
      'CMCON0':0x19,
      'CMCON1':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'WPUA':0x95,
      'IOCA':0x96,
      'EEDATH':0x97,
      'EEADRH':0x98,
      'VRCON':0x99,
      'EEDAT':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f689 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUA':0x95,
      'IOCA':0x96,
      'WDTCON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'SPBRGH':0x9A,
      'BAUDCTL':0x9B,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDAT':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'WPUB':0x115,
      'IOCB':0x116,
      'VRCON':0x118,
      'CM1CON0':0x119,
      'CM2CON0':0x11A,
      'CM2CON1':0x11B,
      'ANSEL':0x11E,
      'ANSELH':0x11F,
      'EECON1':0x18C,
      'EECON2':0x18D,
      'SRCON':0x19E,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f690 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'PWM1CON':0x1C,
      'ECCPAS':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUA':0x95,
      'IOCA':0x96,
      'WDTCON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'SPBRGH':0x9A,
      'BAUDCTL':0x9B,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDAT':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'WPUB':0x115,
      'IOCB':0x116,
      'VRCON':0x118,
      'CM1CON0':0x119,
      'CM2CON0':0x11A,
      'CM2CON1':0x11B,
      'ANSEL':0x11E,
      'ANSELH':0x11F,
      'EECON1':0x18C,
      'EECON2':0x18D,
      'PSTRCON':0x19D,
      'SRCON':0x19E,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f716 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'PWM1CON':0x18,
      'ECCPAS':0x19,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PCON':0x8E,
      'PR2':0x92,
      'ADCON1':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f72 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   data = [ [0x20 , 0x3F], [0xA0 , 0xBF],  ]
   shared = [ 0x40 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'ADCON1':0x9F,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f722 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16f723 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x12F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16f724 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x12F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'ANSELD':0x188,
      'ANSELE':0x189,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16f726 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16f727 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'ANSELD':0x188,
      'ANSELE':0x189,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16f73 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   data = [ [0x20 , 0x7F], [0xA0 , 0xFF],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADCON1':0x9F,
      'PMDATA':0x10C,
      'PMADR':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f737 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'CCPR3L':0x95,
      'CCPR3H':0x96,
      'CCP3CON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADCON2':0x9B,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LVDCON':0x109,
      'PMDATA':0x10C,
      'PMADR':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f74 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   data = [ [0x20 , 0x7F], [0xA0 , 0xFF],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADCON1':0x9F,
      'PMDATA':0x10C,
      'PMADR':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f747 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'CCPR3L':0x95,
      'CCPR3H':0x96,
      'CCP3CON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADCON2':0x9B,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LVDCON':0x109,
      'PMDATA':0x10C,
      'PMADR':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f76 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADCON1':0x9F,
      'PMDATA':0x10C,
      'PMADR':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f767 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'CCPR3L':0x95,
      'CCPR3H':0x96,
      'CCP3CON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADCON2':0x9B,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LVDCON':0x109,
      'PMDATA':0x10C,
      'PMADR':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f77 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADCON1':0x9F,
      'PMDATA':0x10C,
      'PMADR':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f777 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'CCPR3L':0x95,
      'CCPR3H':0x96,
      'CCP3CON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADCON2':0x9B,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LVDCON':0x109,
      'PMDATA':0x10C,
      'PMADR':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f785 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x13,
      'CCPR1H':0x14,
      'CCP1CON':0x15,
      'WDTCON':0x18,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL0':0x91,
      'PR2':0x92,
      'ANSEL1':0x93,
      'WPUA':0x95,
      'IOCA':0x96,
      'REFCON':0x98,
      'VRCON':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'PWMCON1':0x110,
      'PWMCON0':0x111,
      'PWMCLK':0x112,
      'PWMPH1':0x113,
      'PWMPH2':0x114,
      'CM1CON0':0x119,
      'CM2CON0':0x11A,
      'CM2CON1':0x11B,
      'OPA1CON':0x11C,
      'OPA2CON':0x11D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16f818 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x3F], [0xA0 , 0xBF],  ]
   shared = [ 0x40 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f819 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f83 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 512
   eeprom_location = 0x2100
   eeprom_size = 64
   data = [ [0xC , 0x2F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'EEDATA':0x8,
      'EEADR':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'TRISA':0x85,
      'TRISB':0x86,
      'EECON1':0x88,
      'EECON2':0x89,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f84 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 64
   data = [ [0xC , 0x4F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'EEDATA':0x8,
      'EEADR':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'TRISA':0x85,
      'TRISB':0x86,
      'EECON1':0x88,
      'EECON2':0x89,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f84a : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   eeprom_location = 0x2100
   eeprom_size = 64
   data = [ [0xC , 0x4F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'EEDATA':0x8,
      'EEADR':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'TRISA':0x85,
      'TRISB':0x86,
      'EECON1':0x88,
      'EECON2':0x89,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16f87 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'WDTCON':0x105,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f870 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 64
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'PR2':0x92,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f871 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 64
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'PR2':0x92,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f872 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 64
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f873 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x7F], [0xA0 , 0xFF],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f873a : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x7F], [0xA0 , 0xFF],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f874 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x7F], [0xA0 , 0xFF],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f874a : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x7F], [0xA0 , 0xFF],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f876 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f876a : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f877 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f877a : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f88 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'ANSEL':0x9B,
      'CMCON':0x9C,
      'CVRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f882 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 128
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'VRCON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'SPBRGH':0x9A,
      'PWM1CON':0x9B,
      'ECCPAS':0x9C,
      'PSTRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'CM1CON0':0x107,
      'CM2CON0':0x108,
      'CM2CON1':0x109,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'SRCON':0x185,
      'BAUDCTL':0x187,
      'ANSEL':0x188,
      'ANSELH':0x189,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f883 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'VRCON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'SPBRGH':0x9A,
      'PWM1CON':0x9B,
      'ECCPAS':0x9C,
      'PSTRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'CM1CON0':0x107,
      'CM2CON0':0x108,
      'CM2CON1':0x109,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'SRCON':0x185,
      'BAUDCTL':0x187,
      'ANSEL':0x188,
      'ANSELH':0x189,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f884 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'VRCON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'SPBRGH':0x9A,
      'PWM1CON':0x9B,
      'ECCPAS':0x9C,
      'PSTRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'CM1CON0':0x107,
      'CM2CON0':0x108,
      'CM2CON1':0x109,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'SRCON':0x185,
      'BAUDCTL':0x187,
      'ANSEL':0x188,
      'ANSELH':0x189,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f886 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'VRCON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'SPBRGH':0x9A,
      'PWM1CON':0x9B,
      'ECCPAS':0x9C,
      'PSTRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'CM1CON0':0x107,
      'CM2CON0':0x108,
      'CM2CON1':0x109,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'SRCON':0x185,
      'BAUDCTL':0x187,
      'ANSEL':0x188,
      'ANSELH':0x189,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f887 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'SSPCON2':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'VRCON':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'SPBRGH':0x9A,
      'PWM1CON':0x9B,
      'ECCPAS':0x9C,
      'PSTRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'CM1CON0':0x107,
      'CM2CON0':0x108,
      'CM2CON1':0x109,
      'EEDATA':0x10C,
      'EEADR':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'SRCON':0x185,
      'BAUDCTL':0x187,
      'ANSEL':0x188,
      'ANSELH':0x189,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f913 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'CMCON1':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON0':0x9C,
      'VRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LCDCON':0x107,
      'LCDPS':0x108,
      'LVDCON':0x109,
      'EEDATL':0x10C,
      'EEADRL':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'LCDDATA0':0x110,
      'LCDDATA1':0x111,
      'LCDDATA3':0x113,
      'LCDDATA4':0x114,
      'LCDDATA6':0x116,
      'LCDDATA7':0x117,
      'LCDDATA9':0x119,
      'LCDDATA10':0x11A,
      'LCDSE0':0x11C,
      'LCDSE1':0x11D,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f914 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'CMCON1':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON0':0x9C,
      'VRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LCDCON':0x107,
      'LCDPS':0x108,
      'LVDCON':0x109,
      'EEDATL':0x10C,
      'EEADRL':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'LCDDATA0':0x110,
      'LCDDATA1':0x111,
      'LCDDATA2':0x112,
      'LCDDATA3':0x113,
      'LCDDATA4':0x114,
      'LCDDATA5':0x115,
      'LCDDATA6':0x116,
      'LCDDATA7':0x117,
      'LCDDATA8':0x118,
      'LCDDATA9':0x119,
      'LCDDATA10':0x11A,
      'LCDDATA11':0x11B,
      'LCDSE0':0x11C,
      'LCDSE1':0x11D,
      'LCDSE2':0x11E,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f916 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'CMCON1':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON0':0x9C,
      'VRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LCDCON':0x107,
      'LCDPS':0x108,
      'LVDCON':0x109,
      'EEDATL':0x10C,
      'EEADRL':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'LCDDATA0':0x110,
      'LCDDATA1':0x111,
      'LCDDATA3':0x113,
      'LCDDATA4':0x114,
      'LCDDATA6':0x116,
      'LCDDATA7':0x117,
      'LCDDATA9':0x119,
      'LCDDATA10':0x11A,
      'LCDSE0':0x11C,
      'LCDSE1':0x11D,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f917 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'CMCON1':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON0':0x9C,
      'VRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LCDCON':0x107,
      'LCDPS':0x108,
      'LVDCON':0x109,
      'EEDATL':0x10C,
      'EEADRL':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'LCDDATA0':0x110,
      'LCDDATA1':0x111,
      'LCDDATA2':0x112,
      'LCDDATA3':0x113,
      'LCDDATA4':0x114,
      'LCDDATA5':0x115,
      'LCDDATA6':0x116,
      'LCDDATA7':0x117,
      'LCDDATA8':0x118,
      'LCDDATA9':0x119,
      'LCDDATA10':0x11A,
      'LCDDATA11':0x11B,
      'LCDSE0':0x11C,
      'LCDSE1':0x11D,
      'LCDSE2':0x11E,
      'EECON1':0x18C,
      'EECON2':0x18D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16f946 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x16F], [0x1A0 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'CMCON1':0x97,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'CMCON0':0x9C,
      'VRCON':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'WDTCON':0x105,
      'LCDCON':0x107,
      'LCDPS':0x108,
      'LVDCON':0x109,
      'EEDATL':0x10C,
      'EEADRL':0x10D,
      'EEDATH':0x10E,
      'EEADRH':0x10F,
      'LCDDATA0':0x110,
      'LCDDATA1':0x111,
      'LCDDATA2':0x112,
      'LCDDATA3':0x113,
      'LCDDATA4':0x114,
      'LCDDATA5':0x115,
      'LCDDATA6':0x116,
      'LCDDATA7':0x117,
      'LCDDATA8':0x118,
      'LCDDATA9':0x119,
      'LCDDATA10':0x11A,
      'LCDDATA11':0x11B,
      'LCDSE0':0x11C,
      'LCDSE1':0x11D,
      'LCDSE2':0x11E,
      'TRISF':0x185,
      'TRISG':0x187,
      'PORTF':0x188,
      'PORTG':0x189,
      'EECON1':0x18C,
      'EECON2':0x18D,
      'LCDDATA12':0x190,
      'LCDDATA13':0x191,
      'LCDDATA14':0x192,
      'LCDDATA15':0x193,
      'LCDDATA16':0x194,
      'LCDDATA17':0x195,
      'LCDDATA18':0x196,
      'LCDDATA19':0x197,
      'LCDDATA20':0x198,
      'LCDDATA21':0x199,
      'LCDDATA22':0x19A,
      'LCDDATA23':0x19B,
      'LCDSE3':0x19C,
      'LCDSE4':0x19D,
      'LCDSE5':0x19E,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
   } 

class pic_16hv540 : 

   cpu_type = PIC_12
   stack_size = 4
   code_size = 512
   data = [ [0x7 , 0x1F],  ]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
   } 
   shadow_regs = { 
   } 

class pic_16hv610 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 1024
   data = [ [0x40 , 0x6F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'VRCON':0x19,
      'CM1CON0':0x1A,
      'CM2CON0':0x1B,
      'CM2CON1':0x1C,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'WPUA':0x95,
      'IOCA':0x96,
      'SRCON0':0x99,
      'SRCON1':0x9A,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,],
      0x80:[0x0,0x80,],
      
      0x2:[0x2,0x82,],
      0x82:[0x2,0x82,],
      
      0x3:[0x3,0x83,],
      0x83:[0x3,0x83,],
      
      0x4:[0x4,0x84,],
      0x84:[0x4,0x84,],
      
      0xA:[0xA,0x8A,],
      0x8A:[0xA,0x8A,],
      
      0xB:[0xB,0x8B,],
      0x8B:[0xB,0x8B,],
   } 

class pic_16hv616 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x13,
      'CCPR1H':0x14,
      'CCP1CON':0x15,
      'PWM1CON':0x16,
      'ECCPAS':0x17,
      'VRCON':0x19,
      'CM1CON0':0x1A,
      'CM2CON0':0x1B,
      'CM2CON1':0x1C,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCTUNE':0x90,
      'ANSEL':0x91,
      'PR2':0x92,
      'WPUA':0x95,
      'IOCA':0x96,
      'SRCON0':0x99,
      'SRCON1':0x9A,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0xC:[0xC,0x10C,],
      0x10C:[0xC,0x10C,],
      
      0xE:[0xE,0x10E,],
      0x10E:[0xE,0x10E,],
      
      0xE:[0xE,0x10E,],
      0x10E:[0xE,0x10E,],
      
      0xF:[0xF,0x10F,],
      0x10F:[0xF,0x10F,],
      
      0x10:[0x10,0x110,],
      0x110:[0x10,0x110,],
      
      0x11:[0x11,0x111,],
      0x111:[0x11,0x111,],
      
      0x12:[0x12,0x112,],
      0x112:[0x12,0x112,],
      
      0x13:[0x13,0x113,],
      0x113:[0x13,0x113,],
      
      0x13:[0x13,0x113,],
      0x113:[0x13,0x113,],
      
      0x14:[0x14,0x114,],
      0x114:[0x14,0x114,],
      
      0x15:[0x15,0x115,],
      0x115:[0x15,0x115,],
      
      0x16:[0x16,0x116,],
      0x116:[0x16,0x116,],
      
      0x17:[0x17,0x117,],
      0x117:[0x17,0x117,],
      
      0x19:[0x19,0x119,],
      0x119:[0x19,0x119,],
      
      0x1A:[0x1A,0x11A,],
      0x11A:[0x1A,0x11A,],
      
      0x1E:[0x1E,0x11E,],
      0x11E:[0x1E,0x11E,],
      
      0x1F:[0x1F,0x11F,],
      0x11F:[0x1F,0x11F,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
      
      0x8C:[0x8C,0x18C,],
      0x18C:[0x8C,0x18C,],
      
      0x8E:[0x8E,0x18E,],
      0x18E:[0x8E,0x18E,],
      
      0x90:[0x90,0x190,],
      0x190:[0x90,0x190,],
      
      0x91:[0x91,0x191,],
      0x191:[0x91,0x191,],
      
      0x92:[0x92,0x192,],
      0x192:[0x92,0x192,],
      
      0x95:[0x95,0x195,],
      0x195:[0x95,0x195,],
      
      0x96:[0x96,0x196,],
      0x196:[0x96,0x196,],
      
      0x99:[0x99,0x199,],
      0x199:[0x99,0x199,],
      
      0x9A:[0x9A,0x19A,],
      0x19A:[0x9A,0x19A,],
   } 

class pic_16hv785 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   eeprom_location = 0x2100
   eeprom_size = 256
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'CCPR1L':0x13,
      'CCPR1H':0x14,
      'CCP1CON':0x15,
      'WDTCON':0x18,
      'ADRESH':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'PIE1':0x8C,
      'PCON':0x8E,
      'OSCCON':0x8F,
      'OSCTUNE':0x90,
      'ANSEL0':0x91,
      'PR2':0x92,
      'ANSEL1':0x93,
      'WPUA':0x95,
      'IOCA':0x96,
      'REFCON':0x98,
      'VRCON':0x99,
      'EEDATA':0x9A,
      'EEADR':0x9B,
      'EECON1':0x9C,
      'EECON2':0x9D,
      'ADRESL':0x9E,
      'ADCON1':0x9F,
      'PWMCON1':0x110,
      'PWMCON0':0x111,
      'PWMCLK':0x112,
      'PWMPH1':0x113,
      'PWMPH2':0x114,
      'CM1CON0':0x119,
      'CM2CON0':0x11A,
      'CM2CON1':0x11B,
      'OPA1CON':0x11C,
      'OPA2CON':0x11D,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0x5:[0x5,0x105,],
      0x105:[0x5,0x105,],
      
      0x6:[0x6,0x106,],
      0x106:[0x6,0x106,],
      
      0x7:[0x7,0x107,],
      0x107:[0x7,0x107,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
      
      0x85:[0x85,0x185,],
      0x185:[0x85,0x185,],
      
      0x86:[0x86,0x186,],
      0x186:[0x86,0x186,],
      
      0x87:[0x87,0x187,],
      0x187:[0x87,0x187,],
   } 

class pic_16lf722 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 2048
   data = [ [0x20 , 0x6F], [0xA0 , 0xBF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16lf723 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x12F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16lf724 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 4096
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x120 , 0x12F],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'ANSELD':0x188,
      'ANSELE':0x189,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16lf726 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_16lf727 : 

   cpu_type = PIC_14
   stack_size = 8
   code_size = 8192
   data = [ [0x20 , 0x6F], [0xA0 , 0xEF], [0x110 , 0x16F], [0x190 , 0x1EF],  ]
   shared = [ 0x70 , 0x7F]

   fsr_regs = { 
      'INDF':0x0,
      'TMR0':0x1,
      'PCL':0x2,
      'STATUS':0x3,
      'FSR':0x4,
      'PORTA':0x5,
      'PORTB':0x6,
      'PORTC':0x7,
      'PORTD':0x8,
      'PORTE':0x9,
      'PCLATH':0xA,
      'INTCON':0xB,
      'PIR1':0xC,
      'PIR2':0xD,
      'TMR1L':0xE,
      'TMR1H':0xF,
      'T1CON':0x10,
      'TMR2':0x11,
      'T2CON':0x12,
      'SSPBUF':0x13,
      'SSPCON':0x14,
      'CCPR1L':0x15,
      'CCPR1H':0x16,
      'CCP1CON':0x17,
      'RCSTA':0x18,
      'TXREG':0x19,
      'RCREG':0x1A,
      'CCPR2L':0x1B,
      'CCPR2H':0x1C,
      'CCP2CON':0x1D,
      'ADRES':0x1E,
      'ADCON0':0x1F,
      'TRISA':0x85,
      'TRISB':0x86,
      'TRISC':0x87,
      'TRISD':0x88,
      'TRISE':0x89,
      'PIE1':0x8C,
      'PIE2':0x8D,
      'PCON':0x8E,
      'T1GCON':0x8F,
      'OSCCON':0x90,
      'OSCTUNE':0x91,
      'PR2':0x92,
      'SSPADD':0x93,
      'SSPSTAT':0x94,
      'WPUB':0x95,
      'IOCB':0x96,
      'TXSTA':0x98,
      'SPBRG':0x99,
      'APFCON':0x9C,
      'FVRCON':0x9D,
      'ADCON1':0x9F,
      'CPSCON0':0x108,
      'CPSCON1':0x109,
      'PMDATL':0x10C,
      'PMADRL':0x10D,
      'PMDATH':0x10E,
      'PMADRH':0x10F,
      'ANSELA':0x185,
      'ANSELB':0x186,
      'ANSELD':0x188,
      'ANSELE':0x189,
      'PMCON1':0x18C,
   } 
   shadow_regs = { 
      
      0x0:[0x0,0x80,0x100,0x180,],
      0x80:[0x0,0x80,0x100,0x180,],
      0x100:[0x0,0x80,0x100,0x180,],
      0x180:[0x0,0x80,0x100,0x180,],
      
      0x1:[0x1,0x101,],
      0x101:[0x1,0x101,],
      
      0x2:[0x2,0x82,0x102,0x182,],
      0x82:[0x2,0x82,0x102,0x182,],
      0x102:[0x2,0x82,0x102,0x182,],
      0x182:[0x2,0x82,0x102,0x182,],
      
      0x3:[0x3,0x83,0x103,0x183,],
      0x83:[0x3,0x83,0x103,0x183,],
      0x103:[0x3,0x83,0x103,0x183,],
      0x183:[0x3,0x83,0x103,0x183,],
      
      0x4:[0x4,0x84,0x104,0x184,],
      0x84:[0x4,0x84,0x104,0x184,],
      0x104:[0x4,0x84,0x104,0x184,],
      0x184:[0x4,0x84,0x104,0x184,],
      
      0xA:[0xA,0x8A,0x10A,0x18A,],
      0x8A:[0xA,0x8A,0x10A,0x18A,],
      0x10A:[0xA,0x8A,0x10A,0x18A,],
      0x18A:[0xA,0x8A,0x10A,0x18A,],
      
      0xB:[0xB,0x8B,0x10B,0x18B,],
      0x8B:[0xB,0x8B,0x10B,0x18B,],
      0x10B:[0xB,0x8B,0x10B,0x18B,],
      0x18B:[0xB,0x8B,0x10B,0x18B,],
   } 

class pic_18f1220 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 4096
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'LATA':0xF89,
      'LATB':0xF8A,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'BAUDCTL':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCPAS':0xFB6,
      'PWM1CON':0xFB7,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f1230 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 4096
   eeprom_location = 0xF00000
   eeprom_size = 128
   data = [ [0x80 , 0xFF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'OVDCONS':0xF82,
      'OVDCOND':0xF83,
      'DTCON':0xF84,
      'PWMCON1':0xF85,
      'PWMCON0':0xF86,
      'SEVTCMPH':0xF87,
      'SEVTCMPL':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'FLTCONFIG':0xF8B,
      'PDC2H':0xF8C,
      'PDC2L':0xF8D,
      'PDC1H':0xF8E,
      'PDC1L':0xF8F,
      'PDC0H':0xF90,
      'PDC0L':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'PTPERH':0xF95,
      'PTPERL':0xF96,
      'PTMRH':0xF97,
      'PTMRL':0xF98,
      'PTCON1':0xF99,
      'PTCON0':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'BAUDCON':0xFB8,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f1320 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'LATA':0xF89,
      'LATB':0xF8A,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'BAUDCTL':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCPAS':0xFB6,
      'PWM1CON':0xFB7,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f1330 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 128
   data = [ [0x80 , 0xFF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'OVDCONS':0xF82,
      'OVDCOND':0xF83,
      'DTCON':0xF84,
      'PWMCON1':0xF85,
      'PWMCON0':0xF86,
      'SEVTCMPH':0xF87,
      'SEVTCMPL':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'FLTCONFIG':0xF8B,
      'PDC2H':0xF8C,
      'PDC2L':0xF8D,
      'PDC1H':0xF8E,
      'PDC1L':0xF8F,
      'PDC0H':0xF90,
      'PDC0L':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'PTPERH':0xF95,
      'PTPERL':0xF96,
      'PTMRH':0xF97,
      'PTMRL':0xF98,
      'PTCON1':0xF99,
      'PTCON0':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'BAUDCON':0xFB8,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f13k22 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'TSTOUT':0xF65,
      'SRCON0':0xF68,
      'SRCON1':0xF69,
      'CM2CON0':0xF6B,
      'CM2CON1':0xF6C,
      'CM1CON0':0xF6D,
      'SSP1MSK':0xF6F,
      'APFCON':0xF75,
      'SLRCON':0xF76,
      'WPUA':0xF77,
      'WPUB':0xF78,
      'IOCA':0xF79,
      'IOCB':0xF7A,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'VREFCON0':0xFBA,
      'VREFCON1':0xFBB,
      'VREFCON2':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON2':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f13k50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 128
   data = [ [0x60 , 0xFF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'UEP0':0xF53,
      'UEP1':0xF54,
      'UEP2':0xF55,
      'UEP3':0xF56,
      'UEP4':0xF57,
      'UEP5':0xF58,
      'UEP6':0xF59,
      'UEP7':0xF5A,
      'UEIE':0xF5B,
      'UADDR':0xF5C,
      'UFRML':0xF5D,
      'UFRMH':0xF5E,
      'UEIR':0xF5F,
      'UIE':0xF60,
      'UCFG':0xF61,
      'UIR':0xF62,
      'USTAT':0xF63,
      'UCON':0xF64,
      'SRCON0':0xF68,
      'SRCON1':0xF69,
      'CM2CON0':0xF6B,
      'CM2CON1':0xF6C,
      'CM1CON0':0xF6D,
      'SSP1MSK':0xF6F,
      'SLRCON':0xF76,
      'WPUA':0xF77,
      'WPUB':0xF78,
      'IOCA':0xF79,
      'IOCB':0xF7A,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'REFCON0':0xFBA,
      'REFCON1':0xFBB,
      'REFCON2':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON2':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f14k22 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'TSTOUT':0xF65,
      'SRCON0':0xF68,
      'SRCON1':0xF69,
      'CM2CON0':0xF6B,
      'CM2CON1':0xF6C,
      'CM1CON0':0xF6D,
      'SSP1MSK':0xF6F,
      'APFCON':0xF75,
      'SLRCON':0xF76,
      'WPUA':0xF77,
      'WPUB':0xF78,
      'IOCA':0xF79,
      'IOCB':0xF7A,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'VREFCON0':0xFBA,
      'VREFCON1':0xFBB,
      'VREFCON2':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON2':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f14k50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'UEP0':0xF53,
      'UEP1':0xF54,
      'UEP2':0xF55,
      'UEP3':0xF56,
      'UEP4':0xF57,
      'UEP5':0xF58,
      'UEP6':0xF59,
      'UEP7':0xF5A,
      'UEIE':0xF5B,
      'UADDR':0xF5C,
      'UFRML':0xF5D,
      'UFRMH':0xF5E,
      'UEIR':0xF5F,
      'UIE':0xF60,
      'UCFG':0xF61,
      'UIR':0xF62,
      'USTAT':0xF63,
      'UCON':0xF64,
      'SRCON0':0xF68,
      'SRCON1':0xF69,
      'CM2CON0':0xF6B,
      'CM2CON1':0xF6C,
      'CM1CON0':0xF6D,
      'SSP1MSK':0xF6F,
      'SLRCON':0xF76,
      'WPUA':0xF77,
      'WPUB':0xF78,
      'IOCA':0xF79,
      'IOCB':0xF7A,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'REFCON0':0xFBA,
      'REFCON1':0xFBB,
      'REFCON2':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON2':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2220 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 4096
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE2':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2221 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 4096
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2320 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE2':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2321 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2331 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'DFLTCON':0xF60,
      'CAP3CON':0xF61,
      'CAP2CON':0xF62,
      'CAP1CON':0xF63,
      'CAP3BUFL':0xF64,
      'CAP3BUFH':0xF65,
      'CAP2BUFL':0xF66,
      'CAP2BUFH':0xF67,
      'CAP1BUFL':0xF68,
      'CAP1BUFH':0xF69,
      'OVDCONS':0xF6A,
      'OVDCOND':0xF6B,
      'FLTCONFIG':0xF6C,
      'DTCON':0xF6D,
      'PWMCON1':0xF6E,
      'PWMCON0':0xF6F,
      'SEVTCMPH':0xF70,
      'SEVTCMPL':0xF71,
      'PDC3H':0xF72,
      'PDC3L':0xF73,
      'PDC2H':0xF74,
      'PDC2L':0xF75,
      'PDC1H':0xF76,
      'PDC1L':0xF77,
      'PDC0H':0xF78,
      'PDC0L':0xF79,
      'PTPERH':0xF7A,
      'PTPERL':0xF7B,
      'PTMRH':0xF7C,
      'PTMRL':0xF7D,
      'PTCON1':0xF7E,
      'PTCON0':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'TMR5L':0xF87,
      'TMR5H':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'PR5L':0xF90,
      'PR5H':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'ADCHS':0xF99,
      'ADCON3':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'BAUDCTL':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'QEICON':0xFB6,
      'T5CON':0xFB7,
      'ANSEL0':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f23k20 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP1MSK':0xF77,
      'SLRCON':0xF78,
      'CM2CON1':0xF79,
      'CM2CON0':0xF7A,
      'CM1CON0':0xF7B,
      'WPUB':0xF7C,
      'IOCB':0xF7D,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CVRCON2':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2410 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f242 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2420 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2423 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2431 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'DFLTCON':0xF60,
      'CAP3CON':0xF61,
      'CAP2CON':0xF62,
      'CAP1CON':0xF63,
      'CAP3BUFL':0xF64,
      'CAP3BUFH':0xF65,
      'CAP2BUFL':0xF66,
      'CAP2BUFH':0xF67,
      'CAP1BUFL':0xF68,
      'CAP1BUFH':0xF69,
      'OVDCONS':0xF6A,
      'OVDCOND':0xF6B,
      'FLTCONFIG':0xF6C,
      'DTCON':0xF6D,
      'PWMCON1':0xF6E,
      'PWMCON0':0xF6F,
      'SEVTCMPH':0xF70,
      'SEVTCMPL':0xF71,
      'PDC3H':0xF72,
      'PDC3L':0xF73,
      'PDC2H':0xF74,
      'PDC2L':0xF75,
      'PDC1H':0xF76,
      'PDC1L':0xF77,
      'PDC0H':0xF78,
      'PDC0L':0xF79,
      'PTPERH':0xF7A,
      'PTPERL':0xF7B,
      'PTMRH':0xF7C,
      'PTMRL':0xF7D,
      'PTCON1':0xF7E,
      'PTCON0':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'TMR5L':0xF87,
      'TMR5H':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'PR5L':0xF90,
      'PR5H':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'ADCHS':0xF99,
      'ADCON3':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'BAUDCTL':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'QEICON':0xFB6,
      'T5CON':0xFB7,
      'ANSEL0':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2439 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x27F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2450 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'BAUDCON1':0xFB8,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2455 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 24576
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SPPDATA':0xF62,
      'SPPCFG':0xF63,
      'SPPEPS':0xF64,
      'SPPCON':0xF65,
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2458 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 24576
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SPPDATA':0xF62,
      'SPPCFG':0xF63,
      'SPPEPS':0xF64,
      'SPPCON':0xF65,
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f248 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'CANSTATRO4':0xF2E,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'CANSTATRO3':0xF3E,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'CANSTATRO2':0xF4E,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'CANSTATRO1':0xF5E,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2480 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BESL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'BAUDCON':0xFB8,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f24j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f24j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f24j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f24k20 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP1MSK':0xF77,
      'SLRCON':0xF78,
      'CM2CON1':0xF79,
      'CM2CON0':0xF7A,
      'CM1CON0':0xF7B,
      'WPUB':0xF7C,
      'IOCB':0xF7D,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CVRCON2':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2510 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2515 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF7F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f252 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2520 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2523 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2525 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF7F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2539 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x57F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2550 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SPPDATA':0xF62,
      'SPPCFG':0xF63,
      'SPPEPS':0xF64,
      'SPPCON':0xF65,
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2553 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SPPDATA':0xF62,
      'SPPCFG':0xF63,
      'SPPEPS':0xF64,
      'SPPCON':0xF65,
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f258 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'CANSTATRO4':0xF2E,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'CANSTATRO3':0xF3E,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'CANSTATRO2':0xF4E,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'CANSTATRO1':0xF5E,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2580 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BESL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'RB3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'BAUDCON':0xFB8,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2585 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'BAUDCON':0xFB8,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f25j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f25j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f25j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f25k20 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP1MSK':0xF77,
      'SLRCON':0xF78,
      'CM2CON1':0xF79,
      'CM2CON0':0xF7A,
      'CM1CON0':0xF7B,
      'WPUB':0xF7C,
      'IOCB':0xF7D,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CVRCON2':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2610 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF7F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2620 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF7F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2680 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'BAUDCON':0xFB8,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2682 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 81920
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'BAUDCON':0xFB8,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f2685 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98304
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'BAUDCON':0xFB8,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f26j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f26j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f26k20 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP1MSK':0xF77,
      'SLRCON':0xF78,
      'CM2CON1':0xF79,
      'CM2CON0':0xF7A,
      'CM1CON0':0xF7B,
      'WPUB':0xF7C,
      'IOCB':0xF7D,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CVRCON2':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4220 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 4096
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE2':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS':0xFB6,
      'PWM1CON':0xFB7,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4221 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 4096
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4320 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE2':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS':0xFB6,
      'PWM1CON':0xFB7,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4321 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4331 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'DFLTCON':0xF60,
      'CAP3CON':0xF61,
      'CAP2CON':0xF62,
      'CAP1CON':0xF63,
      'CAP3BUFL':0xF64,
      'CAP3BUFH':0xF65,
      'CAP2BUFL':0xF66,
      'CAP2BUFH':0xF67,
      'CAP1BUFL':0xF68,
      'CAP1BUFH':0xF69,
      'OVDCONS':0xF6A,
      'OVDCOND':0xF6B,
      'FLTCONFIG':0xF6C,
      'DTCON':0xF6D,
      'PWMCON1':0xF6E,
      'PWMCON0':0xF6F,
      'SEVTCMPH':0xF70,
      'SEVTCMPL':0xF71,
      'PDC3H':0xF72,
      'PDC3L':0xF73,
      'PDC2H':0xF74,
      'PDC2L':0xF75,
      'PDC1H':0xF76,
      'PDC1L':0xF77,
      'PDC0H':0xF78,
      'PDC0L':0xF79,
      'PTPERH':0xF7A,
      'PTPERL':0xF7B,
      'PTMRH':0xF7C,
      'PTMRL':0xF7D,
      'PTCON1':0xF7E,
      'PTCON0':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'TMR5L':0xF87,
      'TMR5H':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'PR5L':0xF90,
      'PR5H':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'ADCHS':0xF99,
      'ADCON3':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'BAUDCTL':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'QEICON':0xFB6,
      'T5CON':0xFB7,
      'ANSEL0':0xFB8,
      'ANSEL1':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f43k20 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP1MSK':0xF77,
      'SLRCON':0xF78,
      'CM2CON1':0xF79,
      'CM2CON0':0xF7A,
      'CM1CON0':0xF7B,
      'WPUB':0xF7C,
      'IOCB':0xF7D,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CVRCON2':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4410 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f442 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4420 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4423 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4431 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'DFLTCON':0xF60,
      'CAP3CON':0xF61,
      'CAP2CON':0xF62,
      'CAP1CON':0xF63,
      'CAP3BUFL':0xF64,
      'CAP3BUFH':0xF65,
      'CAP2BUFL':0xF66,
      'CAP2BUFH':0xF67,
      'CAP1BUFL':0xF68,
      'CAP1BUFH':0xF69,
      'OVDCONS':0xF6A,
      'OVDCOND':0xF6B,
      'FLTCONFIG':0xF6C,
      'DTCON':0xF6D,
      'PWMCON1':0xF6E,
      'PWMCON0':0xF6F,
      'SEVTCMPH':0xF70,
      'SEVTCMPL':0xF71,
      'PDC3H':0xF72,
      'PDC3L':0xF73,
      'PDC2H':0xF74,
      'PDC2L':0xF75,
      'PDC1H':0xF76,
      'PDC1L':0xF77,
      'PDC0H':0xF78,
      'PDC0L':0xF79,
      'PTPERH':0xF7A,
      'PTPERL':0xF7B,
      'PTMRH':0xF7C,
      'PTMRL':0xF7D,
      'PTCON1':0xF7E,
      'PTCON0':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'TMR5L':0xF87,
      'TMR5H':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'PR5L':0xF90,
      'PR5H':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'ADCHS':0xF99,
      'ADCON3':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'BAUDCTL':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'QEICON':0xFB6,
      'T5CON':0xFB7,
      'ANSEL0':0xFB8,
      'ANSEL1':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4439 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x27F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4450 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'BAUDCON1':0xFB8,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4455 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 24576
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SPPDATA':0xF62,
      'SPPCFG':0xF63,
      'SPPEPS':0xF64,
      'SPPCON':0xF65,
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4458 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 24576
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SPPDATA':0xF62,
      'SPPCFG':0xF63,
      'SPPEPS':0xF64,
      'SPPCON':0xF65,
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f448 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'CANSTATRO4':0xF2E,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'CANSTATRO3':0xF3E,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'CANSTATRO2':0xF4E,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'CANSTATRO1':0xF5E,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS':0xFB6,
      'ECCP1DEL':0xFB7,
      'ECCP1CON':0xFBA,
      'ECCPR1L':0xFBB,
      'ECCPR1H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4480 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'BUFPNT10':0xDE0,
      'BUFPNT32':0xDE1,
      'BUFPNT54':0xDE2,
      'BUFPNT76':0xDE3,
      'BUFPNT98':0xDE4,
      'BUFPNT1110':0xDE5,
      'BUFPNT1312':0xDE6,
      'BUFPNT1514':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BESL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'ECCP1CON':0xFBA,
      'ECCPR1L':0xFBB,
      'ECCPR1H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f44j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'SSP2CON2':0xF85,
      'SSP2CON':0xF86,
      'SSP2STAT':0xF87,
      'SSP2ADD':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'SSP2BUF':0xF8E,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f44j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f44j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f44k20 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP1MSK':0xF77,
      'SLRCON':0xF78,
      'CM2CON1':0xF79,
      'CM2CON0':0xF7A,
      'CM1CON0':0xF7B,
      'WPUB':0xF7C,
      'IOCB':0xF7D,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CVRCON2':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4510 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4515 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF7F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'ECCPR1L':0xFBE,
      'ECCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f452 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4520 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4523 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4525 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF7F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4539 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x57F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4550 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SPPDATA':0xF62,
      'SPPCFG':0xF63,
      'SPPEPS':0xF64,
      'SPPCON':0xF65,
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4553 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SPPDATA':0xF62,
      'SPPCFG':0xF63,
      'SPPEPS':0xF64,
      'SPPCON':0xF65,
      'UFRML':0xF66,
      'UFRMH':0xF67,
      'UIR':0xF68,
      'UIE':0xF69,
      'UEIR':0xF6A,
      'UEIE':0xF6B,
      'USTAT':0xF6C,
      'UCON':0xF6D,
      'UADDR':0xF6E,
      'UCFG':0xF6F,
      'UEP0':0xF70,
      'UEP1':0xF71,
      'UEP2':0xF72,
      'UEP3':0xF73,
      'UEP4':0xF74,
      'UEP5':0xF75,
      'UEP6':0xF76,
      'UEP7':0xF77,
      'UEP8':0xF78,
      'UEP9':0xF79,
      'UEP10':0xF7A,
      'UEP11':0xF7B,
      'UEP12':0xF7C,
      'UEP13':0xF7D,
      'UEP14':0xF7E,
      'UEP15':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f458 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'CANSTATRO4':0xF2E,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'CANSTATRO3':0xF3E,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'CANSTATRO2':0xF4E,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'CANSTATRO1':0xF5E,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS':0xFB6,
      'ECCP1DEL':0xFB7,
      'ECCP1CON':0xFBA,
      'ECCPR1L':0xFBB,
      'ECCPR1H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4580 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'BUFPNT10':0xDE0,
      'BUFPNT32':0xDE1,
      'BUFPNT54':0xDE2,
      'BUFPNT76':0xDE3,
      'BUFPNT98':0xDE4,
      'BUFPNT1110':0xDE5,
      'BUFPNT1312':0xDE6,
      'BUFPNT1514':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BESL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'ECCP1CON':0xFBA,
      'ECCPR1L':0xFBB,
      'ECCPR1H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4585 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'ECCP1CON':0xFBA,
      'ECCPR1L':0xFBB,
      'ECCPR1H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f45j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'SSP2CON2':0xF85,
      'SSP2CON':0xF86,
      'SSP2STAT':0xF87,
      'SSP2ADD':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'SSP2BUF':0xF8E,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f45j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f45j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f45k20 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP1MSK':0xF77,
      'SLRCON':0xF78,
      'CM2CON1':0xF79,
      'CM2CON0':0xF7A,
      'CM1CON0':0xF7B,
      'WPUB':0xF7C,
      'IOCB':0xF7D,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CVRCON2':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4610 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF7F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'ECCPR1L':0xFBE,
      'ECCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4620 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF7F],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4680 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'ECCP1CON':0xFBA,
      'ECCPR1L':0xFBB,
      'ECCPR1H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4682 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 81920
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'ECCP1CON':0xFBA,
      'ECCPR1L':0xFBB,
      'ECCPR1H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f4685 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98304
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP1DEL':0xFB7,
      'BAUDCON':0xFB8,
      'ECCP1CON':0xFBA,
      'ECCPR1L':0xFBB,
      'ECCPR1H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f46j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f46j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f46k20 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP1MSK':0xF77,
      'SLRCON':0xF78,
      'CM2CON1':0xF79,
      'CM2CON0':0xF7A,
      'CM1CON0':0xF7B,
      'WPUB':0xF7C,
      'IOCB':0xF7D,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CVRCON2':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6310 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6390 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'LCDPS':0xF58,
      'LCDCON':0xF59,
      'LCDSE0':0xF5A,
      'LCDSE1':0xF5B,
      'LCDSE2':0xF5C,
      'LCDSE3':0xF5D,
      'LCDD0':0xF60,
      'LCDD1':0xF61,
      'LCDD2':0xF62,
      'LCDD3':0xF63,
      'LCDD4':0xF64,
      'LCDD5':0xF65,
      'LCDD6':0xF66,
      'LCDD7':0xF67,
      'LCDD8':0xF68,
      'LCDD9':0xF69,
      'LCDD10':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'LCDD11':0xF70,
      'LCDD12':0xF71,
      'LCDD13':0xF72,
      'LCDD14':0xF73,
      'LCDD15':0xF74,
      'LCDD16':0xF75,
      'LCDD17':0xF76,
      'LCDD18':0xF77,
      'LCDD19':0xF78,
      'LCDD20':0xF79,
      'LCDD21':0xF7A,
      'LCDD22':0xF7B,
      'LCDD23':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6393 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'LCDPS':0xF58,
      'LCDCON':0xF59,
      'LCDSE0':0xF5A,
      'LCDSE1':0xF5B,
      'LCDSE2':0xF5C,
      'LCDSE3':0xF5D,
      'LCDD0':0xF60,
      'LCDD1':0xF61,
      'LCDD2':0xF62,
      'LCDD3':0xF63,
      'LCDD4':0xF64,
      'LCDD5':0xF65,
      'LCDD6':0xF66,
      'LCDD7':0xF67,
      'LCDD8':0xF68,
      'LCDD9':0xF69,
      'LCDD10':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'LCDD11':0xF70,
      'LCDD12':0xF71,
      'LCDD13':0xF72,
      'LCDD14':0xF73,
      'LCDD15':0xF74,
      'LCDD16':0xF75,
      'LCDD17':0xF76,
      'LCDD18':0xF77,
      'LCDD19':0xF78,
      'LCDD20':0xF79,
      'LCDD21':0xF7A,
      'LCDD22':0xF7B,
      'LCDD23':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f63j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8184
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f63j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8184
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDD5':0xF6B,
      'LCDD6':0xF6C,
      'LCDD7':0xF6D,
      'LCDD8':0xF6E,
      'LCDD9':0xF6F,
      'LCDD10':0xF70,
      'LCDD11':0xF71,
      'LCDD12':0xF72,
      'LCDD13':0xF73,
      'LCDD14':0xF74,
      'LCDD15':0xF75,
      'LCDD16':0xF76,
      'LCDD17':0xF77,
      'LCDD18':0xF78,
      'LCDD19':0xF79,
      'LCDD20':0xF7A,
      'LCDD21':0xF7B,
      'LCDD22':0xF7C,
      'LCDD23':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDD0':0xFBB,
      'LCDD1':0xFBC,
      'LCDD2':0xFBD,
      'LCDD3':0xFBE,
      'LCDD4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6410 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6490 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'LCDPS':0xF58,
      'LCDCON':0xF59,
      'LCDSE0':0xF5A,
      'LCDSE1':0xF5B,
      'LCDSE2':0xF5C,
      'LCDSE3':0xF5D,
      'LCDD0':0xF60,
      'LCDD1':0xF61,
      'LCDD2':0xF62,
      'LCDD3':0xF63,
      'LCDD4':0xF64,
      'LCDD5':0xF65,
      'LCDD6':0xF66,
      'LCDD7':0xF67,
      'LCDD8':0xF68,
      'LCDD9':0xF69,
      'LCDD10':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'LCDD11':0xF70,
      'LCDD12':0xF71,
      'LCDD13':0xF72,
      'LCDD14':0xF73,
      'LCDD15':0xF74,
      'LCDD16':0xF75,
      'LCDD17':0xF76,
      'LCDD18':0xF77,
      'LCDD19':0xF78,
      'LCDD20':0xF79,
      'LCDD21':0xF7A,
      'LCDD22':0xF7B,
      'LCDD23':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6493 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'LCDPS':0xF58,
      'LCDCON':0xF59,
      'LCDSE0':0xF5A,
      'LCDSE1':0xF5B,
      'LCDSE2':0xF5C,
      'LCDSE3':0xF5D,
      'LCDD0':0xF60,
      'LCDD1':0xF61,
      'LCDD2':0xF62,
      'LCDD3':0xF63,
      'LCDD4':0xF64,
      'LCDD5':0xF65,
      'LCDD6':0xF66,
      'LCDD7':0xF67,
      'LCDD8':0xF68,
      'LCDD9':0xF69,
      'LCDD10':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'LCDD11':0xF70,
      'LCDD12':0xF71,
      'LCDD13':0xF72,
      'LCDD14':0xF73,
      'LCDD15':0xF74,
      'LCDD16':0xF75,
      'LCDD17':0xF76,
      'LCDD18':0xF77,
      'LCDD19':0xF78,
      'LCDD20':0xF79,
      'LCDD21':0xF7A,
      'LCDD22':0xF7B,
      'LCDD23':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f64j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f64j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDD5':0xF6B,
      'LCDD6':0xF6C,
      'LCDD7':0xF6D,
      'LCDD8':0xF6E,
      'LCDD9':0xF6F,
      'LCDD10':0xF70,
      'LCDD11':0xF71,
      'LCDD12':0xF72,
      'LCDD13':0xF73,
      'LCDD14':0xF74,
      'LCDD15':0xF75,
      'LCDD16':0xF76,
      'LCDD17':0xF77,
      'LCDD18':0xF78,
      'LCDD19':0xF79,
      'LCDD20':0xF7A,
      'LCDD21':0xF7B,
      'LCDD22':0xF7C,
      'LCDD23':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDD0':0xFBB,
      'LCDD1':0xFBC,
      'LCDD2':0xFBD,
      'LCDD3':0xFBE,
      'LCDD4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6520 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6525 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6527 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6585 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'ECCP1DEL':0xF79,
      'BAUDCON':0xF7E,
      'SPBRGH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f65j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f65j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f65j15 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49144
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f65j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF40,
      'PMSTATH':0xF41,
      'PMEL':0xF42,
      'PMEH':0xF43,
      'PMDIN2L':0xF44,
      'PMDIN2H':0xF45,
      'PMDOUT2L':0xF46,
      'PMDOUT2H':0xF47,
      'PMMODEL':0xF48,
      'PMMODEH':0xF49,
      'PMCONL':0xF4A,
      'PMCONH':0xF4B,
      'UEP0':0xF4C,
      'UEP1':0xF4D,
      'UEP2':0xF4E,
      'UEP3':0xF4F,
      'UEP4':0xF50,
      'UEP5':0xF51,
      'UEP6':0xF52,
      'UEP7':0xF53,
      'UEP8':0xF54,
      'UEP9':0xF55,
      'UEP10':0xF56,
      'UEP11':0xF57,
      'UEP12':0xF58,
      'UEP13':0xF59,
      'UEP14':0xF5A,
      'UEP15':0xF5B,
      'UIE':0xF5C,
      'UEIE':0xF5D,
      'UADDR':0xF5E,
      'UCFG':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCTL2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f65j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDD5':0xF6B,
      'LCDD6':0xF6C,
      'LCDD7':0xF6D,
      'LCDD8':0xF6E,
      'LCDD9':0xF6F,
      'LCDD10':0xF70,
      'LCDD11':0xF71,
      'LCDD12':0xF72,
      'LCDD13':0xF73,
      'LCDD14':0xF74,
      'LCDD15':0xF75,
      'LCDD16':0xF76,
      'LCDD17':0xF77,
      'LCDD18':0xF78,
      'LCDD19':0xF79,
      'LCDD20':0xF7A,
      'LCDD21':0xF7B,
      'LCDD22':0xF7C,
      'LCDD23':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDD0':0xFBB,
      'LCDD1':0xFBC,
      'LCDD2':0xFBD,
      'LCDD3':0xFBE,
      'LCDD4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6620 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6621 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6622 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6627 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98304
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6628 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98304
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6680 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'ECCP1DEL':0xF79,
      'BAUDCON':0xF7E,
      'SPBRGH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f66j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f66j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF5A,
      'PMSTATH':0xF5B,
      'PMEL':0xF5C,
      'PMEH':0xF5D,
      'PMDIN2L':0xF5E,
      'PMDIN2H':0xF5F,
      'PMDOUT2L':0xF60,
      'PMDOUT2H':0xF61,
      'PMMODEL':0xF62,
      'PMMODEH':0xF63,
      'PMCONL':0xF64,
      'PMCONH':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f66j15 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f66j16 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF5A,
      'PMSTATH':0xF5B,
      'PMEL':0xF5C,
      'PMEH':0xF5D,
      'PMDIN2L':0xF5E,
      'PMDIN2H':0xF5F,
      'PMDOUT2L':0xF60,
      'PMDOUT2H':0xF61,
      'PMMODEL':0xF62,
      'PMMODEH':0xF63,
      'PMCONL':0xF64,
      'PMCONH':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f66j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF40,
      'PMSTATH':0xF41,
      'PMEL':0xF42,
      'PMEH':0xF43,
      'PMDIN2L':0xF44,
      'PMDIN2H':0xF45,
      'PMDOUT2L':0xF46,
      'PMDOUT2H':0xF47,
      'PMMODEL':0xF48,
      'PMMODEH':0xF49,
      'PMCONL':0xF4A,
      'PMCONH':0xF4B,
      'UEP0':0xF4C,
      'UEP1':0xF4D,
      'UEP2':0xF4E,
      'UEP3':0xF4F,
      'UEP4':0xF50,
      'UEP5':0xF51,
      'UEP6':0xF52,
      'UEP7':0xF53,
      'UEP8':0xF54,
      'UEP9':0xF55,
      'UEP10':0xF56,
      'UEP11':0xF57,
      'UEP12':0xF58,
      'UEP13':0xF59,
      'UEP14':0xF5A,
      'UEP15':0xF5B,
      'UIE':0xF5C,
      'UEIE':0xF5D,
      'UADDR':0xF5E,
      'UCFG':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCTL2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f66j55 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF40,
      'PMSTATH':0xF41,
      'PMEL':0xF42,
      'PMEH':0xF43,
      'PMDIN2L':0xF44,
      'PMDIN2H':0xF45,
      'PMDOUT2L':0xF46,
      'PMDOUT2H':0xF47,
      'PMMODEL':0xF48,
      'PMMODEH':0xF49,
      'PMCONL':0xF4A,
      'PMCONH':0xF4B,
      'UEP0':0xF4C,
      'UEP1':0xF4D,
      'UEP2':0xF4E,
      'UEP3':0xF4F,
      'UEP4':0xF50,
      'UEP5':0xF51,
      'UEP6':0xF52,
      'UEP7':0xF53,
      'UEP8':0xF54,
      'UEP9':0xF55,
      'UEP10':0xF56,
      'UEP11':0xF57,
      'UEP12':0xF58,
      'UEP13':0xF59,
      'UEP14':0xF5A,
      'UEP15':0xF5B,
      'UIE':0xF5C,
      'UEIE':0xF5D,
      'UADDR':0xF5E,
      'UCFG':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCTL2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f66j60 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f66j65 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f66j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF53],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PADCFG1':0xF54,
      'CTMUICON':0xF55,
      'CTMUCONL':0xF56,
      'CTMUCONH':0xF57,
      'ALRMVALL':0xF58,
      'ALRMVALH':0xF59,
      'ALRMRPT':0xF5A,
      'ALRMCFG':0xF5B,
      'RTCVALL':0xF5C,
      'RTCVALH':0xF5D,
      'RTCCAL':0xF5E,
      'RTCCFG':0xF5F,
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f66j93 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF53],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PADCFG1':0xF54,
      'CTMUICON':0xF55,
      'CTMUCONL':0xF56,
      'CTMUCONH':0xF57,
      'ALRMVALL':0xF58,
      'ALRMVALH':0xF59,
      'ALRMRPT':0xF5A,
      'ALRMCFG':0xF5B,
      'RTCVALL':0xF5C,
      'RTCVALH':0xF5D,
      'RTCCAL':0xF5E,
      'RTCCFG':0xF5F,
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6720 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131072
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6722 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131072
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f6723 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131072
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f67j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f67j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF5A,
      'PMSTATH':0xF5B,
      'PMEL':0xF5C,
      'PMEH':0xF5D,
      'PMDIN2L':0xF5E,
      'PMDIN2H':0xF5F,
      'PMDOUT2L':0xF60,
      'PMDOUT2H':0xF61,
      'PMMODEL':0xF62,
      'PMMODEH':0xF63,
      'PMCONL':0xF64,
      'PMCONH':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f67j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF40,
      'PMSTATH':0xF41,
      'PMEL':0xF42,
      'PMEH':0xF43,
      'PMDIN2L':0xF44,
      'PMDIN2H':0xF45,
      'PMDOUT2L':0xF46,
      'PMDOUT2H':0xF47,
      'PMMODEL':0xF48,
      'PMMODEH':0xF49,
      'PMCONL':0xF4A,
      'PMCONH':0xF4B,
      'UEP0':0xF4C,
      'UEP1':0xF4D,
      'UEP2':0xF4E,
      'UEP3':0xF4F,
      'UEP4':0xF50,
      'UEP5':0xF51,
      'UEP6':0xF52,
      'UEP7':0xF53,
      'UEP8':0xF54,
      'UEP9':0xF55,
      'UEP10':0xF56,
      'UEP11':0xF57,
      'UEP12':0xF58,
      'UEP13':0xF59,
      'UEP14':0xF5A,
      'UEP15':0xF5B,
      'UIE':0xF5C,
      'UEIE':0xF5D,
      'UADDR':0xF5E,
      'UCFG':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCTL2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f67j60 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f67j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF53],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PADCFG1':0xF54,
      'CTMUICON':0xF55,
      'CTMUCONL':0xF56,
      'CTMUCONH':0xF57,
      'ALRMVALL':0xF58,
      'ALRMVALH':0xF59,
      'ALRMRPT':0xF5A,
      'ALRMCFG':0xF5B,
      'RTCVALL':0xF5C,
      'RTCVALH':0xF5D,
      'RTCCAL':0xF5E,
      'RTCCFG':0xF5F,
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f67j93 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF53],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PADCFG1':0xF54,
      'CTMUICON':0xF55,
      'CTMUCONL':0xF56,
      'CTMUCONH':0xF57,
      'ALRMVALL':0xF58,
      'ALRMVALH':0xF59,
      'ALRMRPT':0xF5A,
      'ALRMCFG':0xF5B,
      'RTCVALL':0xF5C,
      'RTCVALH':0xF5D,
      'RTCCAL':0xF5E,
      'RTCCFG':0xF5F,
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8310 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8390 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'LCDPS':0xF58,
      'LCDCON':0xF59,
      'LCDSE0':0xF5A,
      'LCDSE1':0xF5B,
      'LCDSE2':0xF5C,
      'LCDSE3':0xF5D,
      'LCDSE4':0xF5E,
      'LCDSE5':0xF5F,
      'LCDD0':0xF60,
      'LCDD1':0xF61,
      'LCDD2':0xF62,
      'LCDD3':0xF63,
      'LCDD4':0xF64,
      'LCDD5':0xF65,
      'LCDD6':0xF66,
      'LCDD7':0xF67,
      'LCDD8':0xF68,
      'LCDD9':0xF69,
      'LCDD10':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'LCDD11':0xF70,
      'LCDD12':0xF71,
      'LCDD13':0xF72,
      'LCDD14':0xF73,
      'LCDD15':0xF74,
      'LCDD16':0xF75,
      'LCDD17':0xF76,
      'LCDD18':0xF77,
      'LCDD19':0xF78,
      'LCDD20':0xF79,
      'LCDD21':0xF7A,
      'LCDD22':0xF7B,
      'LCDD23':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8393 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'LCDPS':0xF58,
      'LCDCON':0xF59,
      'LCDSE0':0xF5A,
      'LCDSE1':0xF5B,
      'LCDSE2':0xF5C,
      'LCDSE3':0xF5D,
      'LCDSE4':0xF5E,
      'LCDSE5':0xF5F,
      'LCDD0':0xF60,
      'LCDD1':0xF61,
      'LCDD2':0xF62,
      'LCDD3':0xF63,
      'LCDD4':0xF64,
      'LCDD5':0xF65,
      'LCDD6':0xF66,
      'LCDD7':0xF67,
      'LCDD8':0xF68,
      'LCDD9':0xF69,
      'LCDD10':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'LCDD11':0xF70,
      'LCDD12':0xF71,
      'LCDD13':0xF72,
      'LCDD14':0xF73,
      'LCDD15':0xF74,
      'LCDD16':0xF75,
      'LCDD17':0xF76,
      'LCDD18':0xF77,
      'LCDD19':0xF78,
      'LCDD20':0xF79,
      'LCDD21':0xF7A,
      'LCDD22':0xF7B,
      'LCDD23':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f83j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8184
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f83j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8184
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDD5':0xF6B,
      'LCDD6':0xF6C,
      'LCDD7':0xF6D,
      'LCDD8':0xF6E,
      'LCDD9':0xF6F,
      'LCDD10':0xF70,
      'LCDD11':0xF71,
      'LCDD12':0xF72,
      'LCDD13':0xF73,
      'LCDD14':0xF74,
      'LCDD15':0xF75,
      'LCDD16':0xF76,
      'LCDD17':0xF77,
      'LCDD18':0xF78,
      'LCDD19':0xF79,
      'LCDD20':0xF7A,
      'LCDD21':0xF7B,
      'LCDD22':0xF7C,
      'LCDD23':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDD0':0xFBB,
      'LCDD1':0xFBC,
      'LCDD2':0xFBD,
      'LCDD3':0xFBE,
      'LCDD4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8410 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8490 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'LCDPS':0xF58,
      'LCDCON':0xF59,
      'LCDSE0':0xF5A,
      'LCDSE1':0xF5B,
      'LCDSE2':0xF5C,
      'LCDSE3':0xF5D,
      'LCDSE4':0xF5E,
      'LCDSE5':0xF5F,
      'LCDD0':0xF60,
      'LCDD1':0xF61,
      'LCDD2':0xF62,
      'LCDD3':0xF63,
      'LCDD4':0xF64,
      'LCDD5':0xF65,
      'LCDD6':0xF66,
      'LCDD7':0xF67,
      'LCDD8':0xF68,
      'LCDD9':0xF69,
      'LCDD10':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'LCDD11':0xF70,
      'LCDD12':0xF71,
      'LCDD13':0xF72,
      'LCDD14':0xF73,
      'LCDD15':0xF74,
      'LCDD16':0xF75,
      'LCDD17':0xF76,
      'LCDD18':0xF77,
      'LCDD19':0xF78,
      'LCDD20':0xF79,
      'LCDD21':0xF7A,
      'LCDD22':0xF7B,
      'LCDD23':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8493 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'LCDPS':0xF58,
      'LCDCON':0xF59,
      'LCDSE0':0xF5A,
      'LCDSE1':0xF5B,
      'LCDSE2':0xF5C,
      'LCDSE3':0xF5D,
      'LCDSE4':0xF5E,
      'LCDSE5':0xF5F,
      'LCDD0':0xF60,
      'LCDD1':0xF61,
      'LCDD2':0xF62,
      'LCDD3':0xF63,
      'LCDD4':0xF64,
      'LCDD5':0xF65,
      'LCDD6':0xF66,
      'LCDD7':0xF67,
      'LCDD8':0xF68,
      'LCDD9':0xF69,
      'LCDD10':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'LCDD11':0xF70,
      'LCDD12':0xF71,
      'LCDD13':0xF72,
      'LCDD14':0xF73,
      'LCDD15':0xF74,
      'LCDD16':0xF75,
      'LCDD17':0xF76,
      'LCDD18':0xF77,
      'LCDD19':0xF78,
      'LCDD20':0xF79,
      'LCDD21':0xF7A,
      'LCDD22':0xF7B,
      'LCDD23':0xF7C,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'HLVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f84j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f84j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDD5':0xF6B,
      'LCDD6':0xF6C,
      'LCDD7':0xF6D,
      'LCDD8':0xF6E,
      'LCDD9':0xF6F,
      'LCDD10':0xF70,
      'LCDD11':0xF71,
      'LCDD12':0xF72,
      'LCDD13':0xF73,
      'LCDD14':0xF74,
      'LCDD15':0xF75,
      'LCDD16':0xF76,
      'LCDD17':0xF77,
      'LCDD18':0xF78,
      'LCDD19':0xF79,
      'LCDD20':0xF7A,
      'LCDD21':0xF7B,
      'LCDD22':0xF7C,
      'LCDD23':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDD0':0xFBB,
      'LCDD1':0xFBC,
      'LCDD2':0xFBD,
      'LCDD3':0xFBE,
      'LCDD4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8520 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32768
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8525 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8527 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8585 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49152
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'ECCP1DEL':0xF79,
      'BAUDCON':0xF7E,
      'SPBRGH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCPAS1':0xFB6,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f85j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f85j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f85j15 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 49144
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f85j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF40,
      'PMSTATH':0xF41,
      'PMEL':0xF42,
      'PMEH':0xF43,
      'PMDIN2L':0xF44,
      'PMDIN2H':0xF45,
      'PMDOUT2L':0xF46,
      'PMDOUT2H':0xF47,
      'PMMODEL':0xF48,
      'PMMODEH':0xF49,
      'PMCONL':0xF4A,
      'PMCONH':0xF4B,
      'UEP0':0xF4C,
      'UEP1':0xF4D,
      'UEP2':0xF4E,
      'UEP3':0xF4F,
      'UEP4':0xF50,
      'UEP5':0xF51,
      'UEP6':0xF52,
      'UEP7':0xF53,
      'UEP8':0xF54,
      'UEP9':0xF55,
      'UEP10':0xF56,
      'UEP11':0xF57,
      'UEP12':0xF58,
      'UEP13':0xF59,
      'UEP14':0xF5A,
      'UEP15':0xF5B,
      'UIE':0xF5C,
      'UEIE':0xF5D,
      'UADDR':0xF5E,
      'UCFG':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCTL2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f85j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA5':0xF6B,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA11':0xF71,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA17':0xF77,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'LCDDATA23':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8620 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8621 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8622 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8627 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98304
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8628 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98304
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8680 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65536
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RXF6SIDH':0xD60,
      'RXF6SIDL':0xD61,
      'RXF6EIDH':0xD62,
      'RXF6EIDL':0xD63,
      'RXF7SIDH':0xD64,
      'RXF7SIDL':0xD65,
      'RXF7EIDH':0xD66,
      'RXF7EIDL':0xD67,
      'RXF8SIDH':0xD68,
      'RXF8SIDL':0xD69,
      'RXF8EIDH':0xD6A,
      'RXF8EIDL':0xD6B,
      'RXF9SIDH':0xD70,
      'RXF9SIDL':0xD71,
      'RXF9EIDH':0xD72,
      'RXF9EIDL':0xD73,
      'RXF10SIDH':0xD74,
      'RXF10SIDL':0xD75,
      'RXF10EIDH':0xD76,
      'RXF10EIDL':0xD77,
      'RXF11SIDH':0xD78,
      'RXF11SIDL':0xD79,
      'RXF11EIDH':0xD7A,
      'RXF11EIDL':0xD7B,
      'RXF12SIDH':0xD80,
      'RXF12SIDL':0xD81,
      'RXF12EIDH':0xD82,
      'RXF12EIDL':0xD83,
      'RXF13SIDH':0xD84,
      'RXF13SIDL':0xD85,
      'RXF13EIDH':0xD86,
      'RXF13EIDL':0xD87,
      'RXF14SIDH':0xD88,
      'RXF14SIDL':0xD89,
      'RXF14EIDH':0xD8A,
      'RXF14EIDL':0xD8B,
      'RXF15SIDH':0xD90,
      'RXF15SIDL':0xD91,
      'RXF15EIDH':0xD92,
      'RXF15EIDL':0xD93,
      'RXFCON0':0xDD4,
      'RXFCON1':0xDD5,
      'SDFLC':0xDD8,
      'RXFBCON0':0xDE0,
      'RXFBCON1':0xDE1,
      'RXFBCON2':0xDE2,
      'RXFBCON3':0xDE3,
      'RXFBCON4':0xDE4,
      'RXFBCON5':0xDE5,
      'RXFBCON6':0xDE6,
      'RXFBCON7':0xDE7,
      'MSEL0':0xDF0,
      'MSEL1':0xDF1,
      'MSEL2':0xDF2,
      'MSEL3':0xDF3,
      'BSEL0':0xDF8,
      'BIE0':0xDFA,
      'TXBIE':0xDFC,
      'B0CON':0xE20,
      'B0SIDH':0xE21,
      'B0SIDL':0xE22,
      'B0EIDH':0xE23,
      'B0EIDL':0xE24,
      'B0DLC':0xE25,
      'B0D0':0xE26,
      'B0D1':0xE27,
      'B0D2':0xE28,
      'B0D3':0xE29,
      'B0D4':0xE2A,
      'B0D5':0xE2B,
      'B0D6':0xE2C,
      'B0D7':0xE2D,
      'B1CON':0xE30,
      'B1SIDH':0xE31,
      'B1SIDL':0xE32,
      'B1EIDH':0xE33,
      'B1EIDL':0xE34,
      'B1DLC':0xE35,
      'B1D0':0xE36,
      'B1D1':0xE37,
      'B1D2':0xE38,
      'B1D3':0xE39,
      'B1D4':0xE3A,
      'B1D5':0xE3B,
      'B1D6':0xE3C,
      'B1D7':0xE3D,
      'B2CON':0xE40,
      'B2SIDH':0xE41,
      'B2SIDL':0xE42,
      'B2EIDH':0xE43,
      'B2EIDL':0xE44,
      'B2DLC':0xE45,
      'B2D0':0xE46,
      'B2D1':0xE47,
      'B2D2':0xE48,
      'B2D3':0xE49,
      'B2D4':0xE4A,
      'B2D5':0xE4B,
      'B2D6':0xE4C,
      'B2D7':0xE4D,
      'B3CON':0xE50,
      'B3SIDH':0xE51,
      'B3SIDL':0xE52,
      'B3EIDH':0xE53,
      'B3EIDL':0xE54,
      'B3DLC':0xE55,
      'B3D0':0xE56,
      'B3D1':0xE57,
      'B3D2':0xE58,
      'B3D3':0xE59,
      'B3D4':0xE5A,
      'B3D5':0xE5B,
      'B3D6':0xE5C,
      'B3D7':0xE5D,
      'B4CON':0xE60,
      'B4SIDH':0xE61,
      'B4SIDL':0xE62,
      'B4EIDH':0xE63,
      'B4EIDL':0xE64,
      'B4DLC':0xE65,
      'B4D0':0xE66,
      'B4D1':0xE67,
      'B4D2':0xE68,
      'B4D3':0xE69,
      'B4D4':0xE6A,
      'B4D5':0xE6B,
      'B4D6':0xE6C,
      'B4D7':0xE6D,
      'B5CON':0xE70,
      'B5SIDH':0xE71,
      'B5SIDL':0xE72,
      'B5EIDH':0xE73,
      'B5EIDL':0xE74,
      'B5DLC':0xE75,
      'B5D0':0xE76,
      'B5D1':0xE77,
      'B5D2':0xE78,
      'B5D3':0xE79,
      'B5D4':0xE7A,
      'B5D5':0xE7B,
      'B5D6':0xE7C,
      'B5D7':0xE7D,
      'RXF0SIDH':0xF00,
      'RXF0SIDL':0xF01,
      'RXF0EIDH':0xF02,
      'RXF0EIDL':0xF03,
      'RXF1SIDH':0xF04,
      'RXF1SIDL':0xF05,
      'RXF1EIDH':0xF06,
      'RXF1EIDL':0xF07,
      'RXF2SIDH':0xF08,
      'RXF2SIDL':0xF09,
      'RXF2EIDH':0xF0A,
      'RXF2EIDL':0xF0B,
      'RXF3SIDH':0xF0C,
      'RXF3SIDL':0xF0D,
      'RXF3EIDH':0xF0E,
      'RXF3EIDL':0xF0F,
      'RXF4SIDH':0xF10,
      'RXF4SIDL':0xF11,
      'RXF4EIDH':0xF12,
      'RXF4EIDL':0xF13,
      'RXF5SIDH':0xF14,
      'RXF5SIDL':0xF15,
      'RXF5EIDH':0xF16,
      'RXF5EIDL':0xF17,
      'RXM0SIDH':0xF18,
      'RXM0SIDL':0xF19,
      'RXM0EIDH':0xF1A,
      'RXM0EIDL':0xF1B,
      'RXM1SIDH':0xF1C,
      'RXM1SIDL':0xF1D,
      'RXM1EIDH':0xF1E,
      'RXM1EIDL':0xF1F,
      'TXB2CON':0xF20,
      'TXB2SIDH':0xF21,
      'TXB2SIDL':0xF22,
      'TXB2EIDH':0xF23,
      'TXB2EIDL':0xF24,
      'TXB2DLC':0xF25,
      'TXB2D0':0xF26,
      'TXB2D1':0xF27,
      'TXB2D2':0xF28,
      'TXB2D3':0xF29,
      'TXB2D4':0xF2A,
      'TXB2D5':0xF2B,
      'TXB2D6':0xF2C,
      'TXB2D7':0xF2D,
      'TXB1CON':0xF30,
      'TXB1SIDH':0xF31,
      'TXB1SIDL':0xF32,
      'TXB1EIDH':0xF33,
      'TXB1EIDL':0xF34,
      'TXB1DLC':0xF35,
      'TXB1D0':0xF36,
      'TXB1D1':0xF37,
      'TXB1D2':0xF38,
      'TXB1D3':0xF39,
      'TXB1D4':0xF3A,
      'TXB1D5':0xF3B,
      'TXB1D6':0xF3C,
      'TXB1D7':0xF3D,
      'TXB0CON':0xF40,
      'TXB0SIDH':0xF41,
      'TXB0SIDL':0xF42,
      'TXB0EIDH':0xF43,
      'TXB0EIDL':0xF44,
      'TXB0DLC':0xF45,
      'TXB0D0':0xF46,
      'TXB0D1':0xF47,
      'TXB0D2':0xF48,
      'TXB0D3':0xF49,
      'TXB0D4':0xF4A,
      'TXB0D5':0xF4B,
      'TXB0D6':0xF4C,
      'TXB0D7':0xF4D,
      'RXB1CON':0xF50,
      'RXB1SIDH':0xF51,
      'RXB1SIDL':0xF52,
      'RXB1EIDH':0xF53,
      'RXB1EIDL':0xF54,
      'RXB1DLC':0xF55,
      'RXB1D0':0xF56,
      'RXB1D1':0xF57,
      'RXB1D2':0xF58,
      'RXB1D3':0xF59,
      'RXB1D4':0xF5A,
      'RXB1D5':0xF5B,
      'RXB1D6':0xF5C,
      'RXB1D7':0xF5D,
      'RXB0CON':0xF60,
      'RXB0SIDH':0xF61,
      'RXB0SIDL':0xF62,
      'RXB0EIDH':0xF63,
      'RXB0EIDL':0xF64,
      'RXB0DLC':0xF65,
      'RXB0D0':0xF66,
      'RXB0D1':0xF67,
      'RXB0D2':0xF68,
      'RXB0D3':0xF69,
      'RXB0D4':0xF6A,
      'RXB0D5':0xF6B,
      'RXB0D6':0xF6C,
      'RXB0D7':0xF6D,
      'CANSTAT':0xF6E,
      'CANCON':0xF6F,
      'BRGCON1':0xF70,
      'BRGCON2':0xF71,
      'BRGCON3':0xF72,
      'CIOCON':0xF73,
      'COMSTAT':0xF74,
      'RXERRCNT':0xF75,
      'TXERRCNT':0xF76,
      'ECANCON':0xF77,
      'ECCP1DEL':0xF79,
      'BAUDCON':0xF7E,
      'SPBRGH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f86j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f86j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF5A,
      'PMSTATH':0xF5B,
      'PMEL':0xF5C,
      'PMEH':0xF5D,
      'PMDIN2L':0xF5E,
      'PMDIN2H':0xF5F,
      'PMDOUT2L':0xF60,
      'PMDOUT2H':0xF61,
      'PMMODEL':0xF62,
      'PMMODEH':0xF63,
      'PMCONL':0xF64,
      'PMCONH':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f86j15 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f86j16 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF5A,
      'PMSTATH':0xF5B,
      'PMEL':0xF5C,
      'PMEH':0xF5D,
      'PMDIN2L':0xF5E,
      'PMDIN2H':0xF5F,
      'PMDOUT2L':0xF60,
      'PMDOUT2H':0xF61,
      'PMMODEL':0xF62,
      'PMMODEH':0xF63,
      'PMCONL':0xF64,
      'PMCONH':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f86j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF40,
      'PMSTATH':0xF41,
      'PMEL':0xF42,
      'PMEH':0xF43,
      'PMDIN2L':0xF44,
      'PMDIN2H':0xF45,
      'PMDOUT2L':0xF46,
      'PMDOUT2H':0xF47,
      'PMMODEL':0xF48,
      'PMMODEH':0xF49,
      'PMCONL':0xF4A,
      'PMCONH':0xF4B,
      'UEP0':0xF4C,
      'UEP1':0xF4D,
      'UEP2':0xF4E,
      'UEP3':0xF4F,
      'UEP4':0xF50,
      'UEP5':0xF51,
      'UEP6':0xF52,
      'UEP7':0xF53,
      'UEP8':0xF54,
      'UEP9':0xF55,
      'UEP10':0xF56,
      'UEP11':0xF57,
      'UEP12':0xF58,
      'UEP13':0xF59,
      'UEP14':0xF5A,
      'UEP15':0xF5B,
      'UIE':0xF5C,
      'UEIE':0xF5D,
      'UADDR':0xF5E,
      'UCFG':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCTL2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f86j55 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF40,
      'PMSTATH':0xF41,
      'PMEL':0xF42,
      'PMEH':0xF43,
      'PMDIN2L':0xF44,
      'PMDIN2H':0xF45,
      'PMDOUT2L':0xF46,
      'PMDOUT2H':0xF47,
      'PMMODEL':0xF48,
      'PMMODEH':0xF49,
      'PMCONL':0xF4A,
      'PMCONH':0xF4B,
      'UEP0':0xF4C,
      'UEP1':0xF4D,
      'UEP2':0xF4E,
      'UEP3':0xF4F,
      'UEP4':0xF50,
      'UEP5':0xF51,
      'UEP6':0xF52,
      'UEP7':0xF53,
      'UEP8':0xF54,
      'UEP9':0xF55,
      'UEP10':0xF56,
      'UEP11':0xF57,
      'UEP12':0xF58,
      'UEP13':0xF59,
      'UEP14':0xF5A,
      'UEP15':0xF5B,
      'UIE':0xF5C,
      'UEIE':0xF5D,
      'UADDR':0xF5E,
      'UCFG':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCTL2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f86j60 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f86j65 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f86j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF53],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PADCFG1':0xF54,
      'CTMUICON':0xF55,
      'CTMUCONL':0xF56,
      'CTMUCONH':0xF57,
      'ALRMVALL':0xF58,
      'ALRMVALH':0xF59,
      'ALRMRPT':0xF5A,
      'ALRMCFG':0xF5B,
      'RTCVALL':0xF5C,
      'RTCVALH':0xF5D,
      'RTCCAL':0xF5E,
      'RTCCFG':0xF5F,
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA5':0xF6B,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA11':0xF71,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA17':0xF77,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'LCDDATA23':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f86j93 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF53],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PADCFG1':0xF54,
      'CTMUICON':0xF55,
      'CTMUCONL':0xF56,
      'CTMUCONH':0xF57,
      'ALRMVALL':0xF58,
      'ALRMVALH':0xF59,
      'ALRMRPT':0xF5A,
      'ALRMCFG':0xF5B,
      'RTCVALL':0xF5C,
      'RTCVALH':0xF5D,
      'RTCCAL':0xF5E,
      'RTCCFG':0xF5F,
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA5':0xF6B,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA11':0xF71,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA17':0xF77,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'LCDDATA23':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8720 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131072
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8722 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131072
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f8723 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131072
   eeprom_location = 0xF00000
   eeprom_size = 1024
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f87j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'PWM2CON':0xF67,
      'ECCP2AS':0xF68,
      'PWM3CON':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'PWM1CON':0xF79,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'ECCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'ECCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f87j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF5A,
      'PMSTATH':0xF5B,
      'PMEL':0xF5C,
      'PMEH':0xF5D,
      'PMDIN2L':0xF5E,
      'PMDIN2H':0xF5F,
      'PMDOUT2L':0xF60,
      'PMDOUT2H':0xF61,
      'PMMODEL':0xF62,
      'PMMODEH':0xF63,
      'PMCONL':0xF64,
      'PMCONH':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f87j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF3F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PMSTATL':0xF40,
      'PMSTATH':0xF41,
      'PMEL':0xF42,
      'PMEH':0xF43,
      'PMDIN2L':0xF44,
      'PMDIN2H':0xF45,
      'PMDOUT2L':0xF46,
      'PMDOUT2H':0xF47,
      'PMMODEL':0xF48,
      'PMMODEH':0xF49,
      'PMCONL':0xF4A,
      'PMCONH':0xF4B,
      'UEP0':0xF4C,
      'UEP1':0xF4D,
      'UEP2':0xF4E,
      'UEP3':0xF4F,
      'UEP4':0xF50,
      'UEP5':0xF51,
      'UEP6':0xF52,
      'UEP7':0xF53,
      'UEP8':0xF54,
      'UEP9':0xF55,
      'UEP10':0xF56,
      'UEP11':0xF57,
      'UEP12':0xF58,
      'UEP13':0xF59,
      'UEP14':0xF5A,
      'UEP15':0xF5B,
      'UIE':0xF5C,
      'UEIE':0xF5D,
      'UADDR':0xF5E,
      'UCFG':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'PMDIN1L':0xF66,
      'PMDIN1H':0xF67,
      'PMADDRL':0xF68,
      'PMADDRH':0xF69,
      'CMSTATUS':0xF6A,
      'SSP2CON2':0xF6B,
      'SSP2CON':0xF6C,
      'SSP2STAT':0xF6D,
      'SSP2ADD':0xF6E,
      'SSP2BUF':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCTL2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCTL1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'ECCP3CON':0xFB1,
      'CCPR3L':0xFB2,
      'CCPR3H':0xFB3,
      'PWM3CON':0xFB4,
      'ECCP3AS':0xFB5,
      'ECCP2CON':0xFB6,
      'CCPR2L':0xFB7,
      'CCPR2H':0xFB8,
      'PWM2CON':0xFB9,
      'ECCP2AS':0xFBA,
      'ECCP1CON':0xFBB,
      'CCPR1L':0xFBC,
      'CCPR1H':0xFBD,
      'PWM1CON':0xFBE,
      'ECCP1AS':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON1':0xFD1,
      'CM1CON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
      'ANCON0':0xFC1,
      'ANCON1':0xFC2,
   } 
   shadow_regs = { 
   } 

class pic_18f87j60 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f87j90 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF53],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PADCFG1':0xF54,
      'CTMUICON':0xF55,
      'CTMUCONL':0xF56,
      'CTMUCONH':0xF57,
      'ALRMVALL':0xF58,
      'ALRMVALH':0xF59,
      'ALRMRPT':0xF5A,
      'ALRMCFG':0xF5B,
      'RTCVALL':0xF5C,
      'RTCVALH':0xF5D,
      'RTCCAL':0xF5E,
      'RTCCFG':0xF5F,
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA5':0xF6B,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA11':0xF71,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA17':0xF77,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'LCDDATA23':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f87j93 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEFF],  ]
   data = [ [0xF00 , 0xF53],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'PADCFG1':0xF54,
      'CTMUICON':0xF55,
      'CTMUCONL':0xF56,
      'CTMUCONH':0xF57,
      'ALRMVALL':0xF58,
      'ALRMVALH':0xF59,
      'ALRMRPT':0xF5A,
      'ALRMCFG':0xF5B,
      'RTCVALL':0xF5C,
      'RTCVALH':0xF5D,
      'RTCCAL':0xF5E,
      'RTCCFG':0xF5F,
      'RCSTA2':0xF60,
      'TXSTA2':0xF61,
      'TXREG2':0xF62,
      'RCREG2':0xF63,
      'SPBRG2':0xF64,
      'CCP2CON':0xF65,
      'CCPR2L':0xF66,
      'CCPR2H':0xF67,
      'CCP1CON':0xF68,
      'CCPR1L':0xF69,
      'CCPR1H':0xF6A,
      'LCDDATA5':0xF6B,
      'LCDDATA6':0xF6C,
      'LCDDATA7':0xF6D,
      'LCDDATA8':0xF6E,
      'LCDDATA9':0xF6F,
      'LCDDATA10':0xF70,
      'LCDDATA11':0xF71,
      'LCDDATA12':0xF72,
      'LCDDATA13':0xF73,
      'LCDDATA14':0xF74,
      'LCDDATA15':0xF75,
      'LCDDATA16':0xF76,
      'LCDDATA17':0xF77,
      'LCDDATA18':0xF78,
      'LCDDATA19':0xF79,
      'LCDDATA20':0xF7A,
      'LCDDATA21':0xF7B,
      'LCDDATA22':0xF7C,
      'LCDDATA23':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'LCDCON':0xFA8,
      'LCDSE0':0xFA9,
      'LCDPS':0xFAA,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'LCDSE1':0xFB6,
      'LCDSE2':0xFB7,
      'LCDSE3':0xFB8,
      'LCDSE4':0xFB9,
      'LCDSE5':0xFBA,
      'LCDDATA0':0xFBB,
      'LCDDATA1':0xFBC,
      'LCDDATA2':0xFBD,
      'LCDDATA3':0xFBE,
      'LCDDATA4':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LCDREG':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f96j60 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f96j65 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 98296
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18f97j60 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 131064
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xE7F],  ]
   data = [ [0xF00 , 0xF5F],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'MAADR5':0xE80,
      'MAADR6':0xE81,
      'MAADR3':0xE82,
      'MAADR4':0xE83,
      'MAADR1':0xE84,
      'MAADR2':0xE85,
      'MISTAT':0xE8A,
      'EFLOCON':0xE97,
      'EPAUSL':0xE98,
      'EPAUSH':0xE99,
      'MACON1':0xEA0,
      'MACON3':0xEA2,
      'MACON4':0xEA3,
      'MABBIPG':0xEA4,
      'MAIPGL':0xEA6,
      'MAIPGH':0xEA7,
      'MACLCON1':0xEA8,
      'MACLCON2':0xEA9,
      'MAMXFLL':0xEAA,
      'MAMXFLH':0xEAB,
      'MICON':0xEB1,
      'MICMD':0xEB2,
      'MIREGADR':0xEB4,
      'MIWDL':0xEB6,
      'MIWDH':0xEB7,
      'MIRDL':0xEB8,
      'MIRDH':0xEB9,
      'EHT0':0xEC0,
      'EHT1':0xEC1,
      'EHT2':0xEC2,
      'EHT3':0xEC3,
      'EHT4':0xEC4,
      'EHT5':0xEC5,
      'EHT6':0xEC6,
      'EHT7':0xEC7,
      'EPMM0':0xEC8,
      'EPMM1':0xEC9,
      'EPMM2':0xECA,
      'EPMM3':0xECB,
      'EPMM4':0xECC,
      'EPMM5':0xECD,
      'EPMM6':0xECE,
      'EPMM7':0xECF,
      'EPMCSL':0xED0,
      'EPMCSH':0xED1,
      'EPMOL':0xED4,
      'EPMOH':0xED5,
      'ERXFCON':0xED8,
      'EPKTCNT':0xED9,
      'EWRPTL':0xEE2,
      'EWRPTH':0xEE3,
      'ETXSTL':0xEE4,
      'ETXSTH':0xEE5,
      'ETXNDL':0xEE6,
      'ETXNDH':0xEE7,
      'ERXSTL':0xEE8,
      'ERXSTH':0xEE9,
      'ERXNDL':0xEEA,
      'ERXNDH':0xEEB,
      'ERXRDPTL':0xEEC,
      'ERXRDPTH':0xEED,
      'ERXWRPTL':0xEEE,
      'ERXWRPTH':0xEEF,
      'EDMASTL':0xEF0,
      'EDMASTH':0xEF1,
      'EDMANDL':0xEF2,
      'EDMANDH':0xEF3,
      'EDMADSTL':0xEF4,
      'EDMADSTH':0xEF5,
      'EDMASCL':0xEF6,
      'EDMASCH':0xEF7,
      'EIE':0xEFB,
      'ESTAT':0xEFD,
      'ECON2':0xEFE,
      'EIR':0xF60,
      'EDATA':0xF61,
      'SSP2CON2':0xF62,
      'SSP2CON':0xF63,
      'SSP2STAT':0xF64,
      'SSP2ADD':0xF65,
      'SSP2BUF':0xF66,
      'ECCP2DEL':0xF67,
      'ECCP2AS':0xF68,
      'ECCP3DEL':0xF69,
      'ECCP3AS':0xF6A,
      'RCSTA2':0xF6B,
      'TXSTA2':0xF6C,
      'TXREG2':0xF6D,
      'RCREG2':0xF6E,
      'SPBRG2':0xF6F,
      'CCP5CON':0xF70,
      'CCPR5L':0xF71,
      'CCPR5H':0xF72,
      'CCP4CON':0xF73,
      'CCPR4L':0xF74,
      'CCPR4H':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'ECCP1DEL':0xF79,
      'ERDPTL':0xF7A,
      'ERDPTH':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'PORTF':0xF85,
      'PORTG':0xF86,
      'PORTH':0xF87,
      'PORTJ':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'LATF':0xF8E,
      'LATG':0xF8F,
      'LATH':0xF90,
      'LATJ':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'TRISF':0xF97,
      'TRISG':0xF98,
      'TRISH':0xF99,
      'TRISJ':0xF9A,
      'OSCTUNE':0xF9B,
      'MEMCON':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA1':0xFAB,
      'TXSTA1':0xFAC,
      'TXREG1':0xFAD,
      'RCREG1':0xFAE,
      'SPBRG1':0xFAF,
      'PSPCON':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'CCP3CON':0xFB7,
      'CCPR3L':0xFB8,
      'CCPR3H':0xFB9,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'ECON1':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf13k22 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'TSTOUT':0xF65,
      'SRCON0':0xF68,
      'SRCON1':0xF69,
      'CM2CON0':0xF6B,
      'CM2CON1':0xF6C,
      'CM1CON0':0xF6D,
      'SSP1MSK':0xF6F,
      'APFCON':0xF75,
      'SLRCON':0xF76,
      'WPUA':0xF77,
      'WPUB':0xF78,
      'IOCA':0xF79,
      'IOCB':0xF7A,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'VREFCON0':0xFBA,
      'VREFCON1':0xFBB,
      'VREFCON2':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON2':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf13k50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 8192
   eeprom_location = 0xF00000
   eeprom_size = 128
   data = [ [0x60 , 0xFF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'UEP0':0xF53,
      'UEP1':0xF54,
      'UEP2':0xF55,
      'UEP3':0xF56,
      'UEP4':0xF57,
      'UEP5':0xF58,
      'UEP6':0xF59,
      'UEP7':0xF5A,
      'UEIE':0xF5B,
      'UADDR':0xF5C,
      'UFRML':0xF5D,
      'UFRMH':0xF5E,
      'UEIR':0xF5F,
      'UIE':0xF60,
      'UCFG':0xF61,
      'UIR':0xF62,
      'USTAT':0xF63,
      'UCON':0xF64,
      'SRCON0':0xF68,
      'SRCON1':0xF69,
      'CM2CON0':0xF6B,
      'CM2CON1':0xF6C,
      'CM1CON0':0xF6D,
      'SSP1MSK':0xF6F,
      'SLRCON':0xF76,
      'WPUA':0xF77,
      'WPUB':0xF78,
      'IOCA':0xF79,
      'IOCB':0xF7A,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'REFCON0':0xFBA,
      'REFCON1':0xFBB,
      'REFCON2':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON2':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf14k22 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'TSTOUT':0xF65,
      'SRCON0':0xF68,
      'SRCON1':0xF69,
      'CM2CON0':0xF6B,
      'CM2CON1':0xF6C,
      'CM1CON0':0xF6D,
      'SSP1MSK':0xF6F,
      'APFCON':0xF75,
      'SLRCON':0xF76,
      'WPUA':0xF77,
      'WPUB':0xF78,
      'IOCA':0xF79,
      'IOCB':0xF7A,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'VREFCON0':0xFBA,
      'VREFCON1':0xFBB,
      'VREFCON2':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON2':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf14k50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16384
   eeprom_location = 0xF00000
   eeprom_size = 256
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'UEP0':0xF53,
      'UEP1':0xF54,
      'UEP2':0xF55,
      'UEP3':0xF56,
      'UEP4':0xF57,
      'UEP5':0xF58,
      'UEP6':0xF59,
      'UEP7':0xF5A,
      'UEIE':0xF5B,
      'UADDR':0xF5C,
      'UFRML':0xF5D,
      'UFRMH':0xF5E,
      'UEIR':0xF5F,
      'UIE':0xF60,
      'UCFG':0xF61,
      'UIR':0xF62,
      'USTAT':0xF63,
      'UCON':0xF64,
      'SRCON0':0xF68,
      'SRCON1':0xF69,
      'CM2CON0':0xF6B,
      'CM2CON1':0xF6C,
      'CM1CON0':0xF6D,
      'SSP1MSK':0xF6F,
      'SLRCON':0xF76,
      'WPUA':0xF77,
      'WPUB':0xF78,
      'IOCA':0xF79,
      'IOCB':0xF7A,
      'ANSEL':0xF7E,
      'ANSELH':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'EEDATA':0xFA8,
      'EEADR':0xFA9,
      'EEADRH':0xFAA,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'T3CON':0xFB1,
      'TMR3L':0xFB2,
      'TMR3H':0xFB3,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCON':0xFB8,
      'PSTRCON':0xFB9,
      'REFCON0':0xFBA,
      'REFCON1':0xFBB,
      'REFCON2':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON2':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf24j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCTL':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf24j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf24j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf25j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCTL':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'CCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'LVDCON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf25j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf25j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf26j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf26j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf44j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'SSP2CON2':0xF85,
      'SSP2CON':0xF86,
      'SSP2STAT':0xF87,
      'SSP2ADD':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'SSP2BUF':0xF8E,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCTL':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf44j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf44j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 16376
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf45j10 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x80 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF],  ]
   shared = [ 0x0 , 0x7F]

   fsr_regs = { 
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'SSP2CON2':0xF85,
      'SSP2CON':0xF86,
      'SSP2STAT':0xF87,
      'SSP2ADD':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'SSP2BUF':0xF8E,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'OSCTUNE':0xF9B,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'RCSTA':0xFAB,
      'TXSTA':0xFAC,
      'TXREG':0xFAD,
      'RCREG':0xFAE,
      'SPBRG':0xFAF,
      'SPBRGH':0xFB0,
      'CMCON':0xFB4,
      'CVRCON':0xFB5,
      'ECCP1AS':0xFB6,
      'PWM1CON':0xFB7,
      'BAUDCTL':0xFB8,
      'CCP2CON':0xFBA,
      'CCPR2L':0xFBB,
      'CCPR2H':0xFBC,
      'ECCP1CON':0xFBD,
      'CCPR1L':0xFBE,
      'CCPR1H':0xFBF,
      'ADCON2':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'WDTCON':0xFD1,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf45j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf45j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 32760
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf46j11 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR14':0xED4,
      'RPOR15':0xED5,
      'RPOR16':0xED6,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_18lf46j50 : 

   cpu_type = PIC_16
   stack_size = 31
   code_size = 65528
   data = [ [0x60 , 0xFF], [0x100 , 0x1FF], [0x200 , 0x2FF], [0x300 , 0x3FF], [0x400 , 0x4FF],  ]
   data = [ [0x500 , 0x5FF], [0x600 , 0x6FF], [0x700 , 0x7FF], [0x800 , 0x8FF], [0x900 , 0x9FF],  ]
   data = [ [0xA00 , 0xAFF], [0xB00 , 0xBFF], [0xC00 , 0xCFF], [0xD00 , 0xDFF], [0xE00 , 0xEBF],  ]
   shared = [ 0x0 , 0x5F]

   fsr_regs = { 
      'RPOR0':0xEC6,
      'RPOR1':0xEC7,
      'RPOR2':0xEC8,
      'RPOR3':0xEC9,
      'RPOR4':0xECA,
      'RPOR5':0xECB,
      'RPOR6':0xECC,
      'RPOR7':0xECD,
      'RPOR8':0xECE,
      'RPOR9':0xECF,
      'RPOR10':0xED0,
      'RPOR11':0xED1,
      'RPOR12':0xED2,
      'RPOR13':0xED3,
      'RPOR17':0xED7,
      'RPOR18':0xED8,
      'RPOR19':0xED9,
      'RPOR20':0xEDA,
      'RPOR21':0xEDB,
      'RPOR22':0xEDC,
      'RPOR23':0xEDD,
      'RPOR24':0xEDE,
      'RPINR1':0xEE7,
      'RPINR2':0xEE8,
      'RPINR3':0xEE9,
      'RPINR4':0xEEA,
      'RPINR6':0xEEC,
      'RPINR7':0xEED,
      'RPINR8':0xEEE,
      'RPINR12':0xEF2,
      'RPINR13':0xEF3,
      'RPINR16':0xEF6,
      'RPINR17':0xEF7,
      'RPINR21':0xEFB,
      'RPINR22':0xEFC,
      'RPINR23':0xEFD,
      'RPINR24':0xEFE,
      'PPSCON':0xEFF,
      'UEP0':0xF26,
      'UEP1':0xF27,
      'UEP2':0xF28,
      'UEP3':0xF29,
      'UEP4':0xF2A,
      'UEP5':0xF2B,
      'UEP6':0xF2C,
      'UEP7':0xF2D,
      'UEP8':0xF2E,
      'UEP9':0xF2F,
      'UEP10':0xF30,
      'UEP11':0xF31,
      'UEP12':0xF32,
      'UEP13':0xF33,
      'UEP14':0xF34,
      'UEP15':0xF35,
      'UIE':0xF36,
      'UEIE':0xF37,
      'UADDR':0xF38,
      'UCFG':0xF39,
      'PADCFG1':0xF3C,
      'REFOCON':0xF3D,
      'RTCCAL':0xF3E,
      'RTCCFG':0xF3F,
      'ODCON3':0xF40,
      'ODCON2':0xF41,
      'ODCON1':0xF42,
      'ANCON0':0xF48,
      'ANCON1':0xF49,
      'DSWAKEL':0xF4A,
      'DSWAKEH':0xF4B,
      'DSCONL':0xF4C,
      'DSCONH':0xF4D,
      'DSGPR0':0xF4E,
      'DSGPR1':0xF4F,
      'TCLKCON':0xF52,
      'CVRCON':0xF53,
      'PMSTATL':0xF54,
      'PMSTATH':0xF55,
      'PMEL':0xF56,
      'PMEH':0xF57,
      'PMDIN2L':0xF58,
      'PMDIN2H':0xF59,
      'PMDOUT2L':0xF5A,
      'PMDOUT2H':0xF5B,
      'PMMODEL':0xF5C,
      'PMMODEH':0xF5D,
      'PMCONL':0xF5E,
      'PMCONH':0xF5F,
      'UFRML':0xF60,
      'UFRMH':0xF61,
      'UIR':0xF62,
      'UEIR':0xF63,
      'USTAT':0xF64,
      'UCON':0xF65,
      'DMABCH':0xF66,
      'DMABCL':0xF67,
      'RXADDRH':0xF68,
      'RXADDRL':0xF69,
      'TXADDRH':0xF6A,
      'TXADDRL':0xF6B,
      'PMDIN1L':0xF6C,
      'PMDIN1H':0xF6D,
      'PMADDRL':0xF6E,
      'PMDOUT1L':0xF6E,
      'PMADDRH':0xF6F,
      'PMDOUT1H':0xF6F,
      'CMSTAT':0xF70,
      'SSP2CON2':0xF71,
      'SSP2CON':0xF72,
      'SSP2STAT':0xF73,
      'SSP2ADD':0xF74,
      'SSP2BUF':0xF75,
      'T4CON':0xF76,
      'PR4':0xF77,
      'TMR4':0xF78,
      'T3CON':0xF79,
      'TMR3L':0xF7A,
      'TMR3H':0xF7B,
      'BAUDCON2':0xF7C,
      'SPBRGH2':0xF7D,
      'BAUDCON1':0xF7E,
      'SPBRGH1':0xF7F,
      'PORTA':0xF80,
      'PORTB':0xF81,
      'PORTC':0xF82,
      'PORTD':0xF83,
      'PORTE':0xF84,
      'HLVDCON':0xF85,
      'DMACON2':0xF86,
      'DMACON1':0xF88,
      'LATA':0xF89,
      'LATB':0xF8A,
      'LATC':0xF8B,
      'LATD':0xF8C,
      'LATE':0xF8D,
      'ALRMVALL':0xF8E,
      'ALRMVALH':0xF8F,
      'ALRMRPT':0xF90,
      'ALRMCFG':0xF91,
      'TRISA':0xF92,
      'TRISB':0xF93,
      'TRISC':0xF94,
      'TRISD':0xF95,
      'TRISE':0xF96,
      'T3GCON':0xF97,
      'RTCVALL':0xF98,
      'RTCVALH':0xF99,
      'T1GCON':0xF9A,
      'OSCTUNE':0xF9B,
      'RCSTA2':0xF9C,
      'PIE1':0xF9D,
      'PIR1':0xF9E,
      'IPR1':0xF9F,
      'PIE2':0xFA0,
      'PIR2':0xFA1,
      'IPR2':0xFA2,
      'PIE3':0xFA3,
      'PIR3':0xFA4,
      'IPR3':0xFA5,
      'EECON1':0xFA6,
      'EECON2':0xFA7,
      'TXSTA2':0xFA8,
      'TXREG2':0xFA9,
      'RCREG2':0xFAA,
      'SPBRG2':0xFAB,
      'RCSTA1':0xFAC,
      'TXSTA1':0xFAD,
      'TXREG1':0xFAE,
      'RCREG1':0xFAF,
      'SPBRG1':0xFB0,
      'CTMUICON':0xFB1,
      'CTMUCONL':0xFB2,
      'CTMUCONH':0xFB3,
      'CCP2CON':0xFB4,
      'CCPR2L':0xFB5,
      'CCPR2H':0xFB6,
      'ECCP2DEL':0xFB7,
      'ECCP2AS':0xFB8,
      'PSTR2CON':0xFB9,
      'CCP1CON':0xFBA,
      'CCPR1L':0xFBB,
      'CCPR1H':0xFBC,
      'ECCP1DEL':0xFBD,
      'ECCP1AS':0xFBE,
      'PSTR1CON':0xFBF,
      'WDTCON':0xFC0,
      'ADCON1':0xFC1,
      'ADCON0':0xFC2,
      'ADRESL':0xFC3,
      'ADRESH':0xFC4,
      'SSP1CON2':0xFC5,
      'SSP1CON':0xFC6,
      'SSP1STAT':0xFC7,
      'SSP1ADD':0xFC8,
      'SSP1BUF':0xFC9,
      'T2CON':0xFCA,
      'PR2':0xFCB,
      'TMR2':0xFCC,
      'T1CON':0xFCD,
      'TMR1L':0xFCE,
      'TMR1H':0xFCF,
      'RCON':0xFD0,
      'CM2CON':0xFD1,
      'CM1CON':0xFD2,
      'OSCCON':0xFD3,
      'T0CON':0xFD5,
      'TMR0L':0xFD6,
      'TMR0H':0xFD7,
      'STATUS':0xFD8,
      'FSR2L':0xFD9,
      'FSR2H':0xFDA,
      'PLUSW2':0xFDB,
      'PREINC2':0xFDC,
      'POSTDEC2':0xFDD,
      'POSTINC2':0xFDE,
      'INDF2':0xFDF,
      'BSR':0xFE0,
      'FSR1L':0xFE1,
      'FSR1H':0xFE2,
      'PLUSW1':0xFE3,
      'PREINC1':0xFE4,
      'POSTDEC1':0xFE5,
      'POSTINC1':0xFE6,
      'INDF1':0xFE7,
      'WREG':0xFE8,
      'FSR0L':0xFE9,
      'FSR0H':0xFEA,
      'PLUSW0':0xFEB,
      'PREINC0':0xFEC,
      'POSTDEC0':0xFED,
      'POSTINC0':0xFEE,
      'INDF0':0xFEF,
      'INTCON3':0xFF0,
      'INTCON2':0xFF1,
      'INTCON':0xFF2,
      'PRODL':0xFF3,
      'PRODH':0xFF4,
      'TABLAT':0xFF5,
      'TBLPTRL':0xFF6,
      'TBLPTRH':0xFF7,
      'TBLPTRU':0xFF8,
      'PCL':0xFF9,
      'PCLATH':0xFFA,
      'PCLATU':0xFFB,
      'STKPTR':0xFFC,
      'TOSL':0xFFD,
      'TOSH':0xFFE,
      'TOSU':0xFFF,
   } 
   shadow_regs = { 
   } 

class pic_chipdef_jallib : 


   fsr_regs = { 
   } 
   shadow_regs = { 
   } 

def PicFactory( strName ): 
   return globals()[strName]() 
